Datasheet

AD9558 Data Sheet
Rev. B | Page 52 of 104
CS
SCLK
SDIO
t
HIGH
t
LOW
t
CLK
t
S
t
DS
t
DH
t
C
BIT N BIT N + 1
09758-034
Figure 51. Serial Control Port Timing—Write
Table 28. Serial Control Port Timing
Parameter Description
t
DS
Setup time between data and the rising edge of SCLK
t
DH
Hold time between data and the rising edge of SCLK
t
CLK
Period of the clock
t
S
Setup time between the AACS
EE
AA
falling edge and the SCLK rising edge (start of the communication cycle)
t
C
Setup time between the SCLK rising edge and AACS
EE
AA
rising edge (end of the communication cycle)
t
HIGH
Minimum period that SCLK should be in a logic high state
t
LOW
Minimum period that SCLK should be in a logic low state
t
DV
SCLK to valid SDIO and SDO (see Figure 49)