Datasheet

Data Sheet AD9558
Rev. B | Page 67 of 104
Reg
Addr
(Hex)
Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def
Profile C (for REFC)
0x0780 L Reference
period (up to
1.1 ms)
Nominal period (fs), Bits[7:0] (default: 125 µs = 1/(8 kHz) for default system clock setting)
C9
0x0781 L
Nominal period (fs), Bits[15:8]
EA
0x0782 L
Nominal period (fs), Bits[23:16]
10
0x0783 L
Nominal period (fs), Bits[31:24]
03
0x0784 L
Nominal period (fs), Bits[39:32]
00
0x0785 L Frequency
tolerance
Inner tolerance (1 ppm), Bits[7:0] (for reference invalid to valid; 50% down to 1 ppm) (default: 5%)
14
0x0786 L
Inner tolerance (1 ppm), Bits[15:8] (for reference invalid to valid; 50% down to 1 ppm)
00
0x0787 L Reserved
Inner tolerance, Bits[19:16]
00
0x0788 L
Outer tolerance (1 ppm), Bits[7:0] (for reference valid to invalid; 50% down to 1 ppm] (default: 10%)
0A
0x0789 L
Outer tolerance (1 ppm), Bits[15:8] (for reference valid to invalid; 50% down to 1 ppm)
00
0x078A L Reserved
Outer tolerance, Bits[19:16]
00
0x078B L Validation
Validation timer (ms), Bits[7:0] (up to 65.5 seconds)
0A
0x078C L
Validation timer (ms), Bits[15:8] (up to 65.5 seconds)
00
0x078D L Reserved 00
0x078E L Select base
loop filter
Reserved
Sel high PM
base loop filt
00
0x078F L DPLL loop BW Digital PLL loop BW scaling factor[7:0] (default: 0x01F4 = 50 Hz) F4
0x0790 L Digital PLL loop BW scaling factor[15:8] 01
0x0791 L Reserved BW scaling
factor[16]
00
0x0792 L DPLL
R divider
(20 bits)
R divider[7:0] C5
0x0793 L R divider[15:8] 00
0x0794 L Reserved Enable REFC
divide-by-2
R divider[19:16] 00
0x0795 DPLL
N divider
(17 bits)
Digital PLL feedback divider—Integer Part N1[7:0] 6B
0x0796
Digital PLL feedback divider—Integer Part N1[15:8]
07
0x0797 Reserved Digital PLL
feedback
divider—
Integer Part
N1[16]
00
0x0798 DPLL
fractional
feedback
divider
(24 bits)
Digital PLL fractional feedback divider—FRAC1[7:0] 04
0x0799 Digital PLL fractional feedback divider—FRAC1[15:8] 00
0x079A Digital PLL fractional feedback divider—FRAC1[23:16] 00
0x079B DPLL
fractional
feedback
divider
modulus
(24 bits)
Digital PLL feedback divider modulus—MOD1[7:0] 05
0x079C
Digital PLL feedback divider modulus—MOD1[15:8]
00
0x079D Digital PLL feedback divider modulus—MOD1[23:16] 00
0x079E L Lock detectors Phase lock threshold (ps), Bits[7:0] BC
0x079F L Phase lock threshold (ps), Bits[15:8] 02
0x07A0 L Phase lock fill rate[7:0] 0A
0x07A1 L Phase lock drain rate[7:0] 0A
0x07A2 L Frequency lock threshold[7:0] BC
0x07A3 L Frequency lock threshold[15:8] 02
0x07A4 L Frequency lock threshold[23:16] 00
0x07A5 L Frequency lock fill rate[7:0] 0A
0x07A6 L Frequency lock drain rate[7:0] 0A