Datasheet

AD9608
Rev. 0 | Page 4 of 40
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless
otherwise noted.
Table 1.
AD9608-105 AD9608-125
Parameter Temp Min Typ Max Min Typ Max Unit
RESOLUTION Full 10 10 Bits
ACCURACY
No Missing Codes Full Guaranteed Guaranteed
Offset Error Full −1.0 −0.3 +0.4 −1.0 −0.3 +0.4 % FSR
Gain Error Full −2.8 ±1.5 +9.0 −2.8 ±1.5 +9.0 % FSR
Differential Nonlinearity (DNL)
1
Full ±0.35 ±0.35 LSB
25°C ±0.12 ±0.13 LSB
Integral Nonlinearity (INL)
1
Full ±0.40 ±0.40 LSB
25°C ±0.14 ±0.14 LSB
MATCHING CHARACTERISTIC
Offset Error Full ±0.1 ±1.0 ±0.1 ±1.0 % FSR
Gain Error Full ±0.5 ±6.5 ±0.5 ±6.5 % FSR
TEMPERATURE DRIFT
Offset Error Full ±2 ±2 ppm/°C
Gain Error Full ±50 ±50 ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode) Full 0.98 1.00 1.02 0.98 1.00 1.02 V
Load Regulation Error at 1.0 mA Full 2 2 mV
INPUT REFERRED NOISE
VREF = 1.0 V 25°C 0.08 0.08 LSB rms
ANALOG INPUT
Input Span, VREF = 1.0 V Full 2 2 V p-p
Input Capacitance
2
Full 5 5 pF
Input Resistance (Differential) Full 7.5 7.5 kΩ
Input Common-Mode Voltage Full 0.9 0.9 V
Input Common-Mode Range Full 0.5 1.3 0.5 1.3 V
POWER SUPPLIES
Supply Voltage
AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V
Supply Current
I
AVDD
1
Full 76.8 82.0 87.7 93.0 mA
I
DRVDD
1
(1.8 V CMOS)
Full 14.7 17.4 mA
I
DRVDD
1
(1.8 V LVDS)
Full 48.5 49.7 mA
POWER CONSUMPTION
DC Input Full 125 141 mW
Sine Wave Input
1
(DRVDD = 1.8 V CMOS Output Mode)
Full 165 174 189 199 mW
Sine Wave Input
1
(DRVDD = 1.8 V LVDS Output Mode)
Full 226 247 mW
Standby Power
3
Full
108
120 mW
Power-Down Power Full 2.0 2.0 mW
1
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
2
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3
Standby power is measured with a dc input and with the CLK± pins active (1.8 V CMOS mode).