Datasheet

AD9608
Rev. 0 | Page 9 of 40
t
PD
t
SKEW
t
CH
t
DCO
t
CLK
CH A
N – 16
CH B
N – 16
CH A
N – 15
CH B
N – 15
CH A
N – 14
CH B
N – 14
CH A
N – 13
CH B
N – 13
CH A
N – 12
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
VIN
CLK+
CLK–
DCO–
DCO+
D0+ (LSB)
PARALLEL
INTERLEAVED
MODE
D0– (LSB)
D9+ (MSB)
D9– (MSB)
t
A
CH A
N – 16
CH B
N – 16
CH A
N – 15
CH B
N – 15
CH A
N – 14
CH B
N – 14
CH A
N – 13
CH B
N – 13
CH A
N – 12
CH A0
N – 16
CH A1
N – 16
CH A0
N – 15
CH A1
N – 15
CH A0
N – 14
CH A1
N – 14
CH A0
N – 13
CH A1
N – 13
CH A0
N – 12
D1+/D0+ (LSB)
CHANNEL
MULTIPLEXED
MODE
CHANNEL A
D1–/D0– (LSB)
D9+/D8+ (MSB)
D9–/D8– (MSB)
CH A8
N – 16
CH A9
N – 16
CH A8
N – 15
CH A9
N – 15
CH A8
N – 14
CH A9
N – 14
CH A8
N – 13
CH A9
N – 13
CH A8
N – 12
CH B0
N – 16
CH B1
N – 16
CH B0
N – 15
CH B1
N – 15
CH B0
N – 14
CH B1
N – 14
CH B0
N – 13
CH B1
N – 13
CH B0
N – 12
D1+/D0+ (LSB)
CHANNEL
MULTIPLEXED
MODE
CHANNEL B
D1–/D0– (LSB)
D9+/D8+ (MSB)
D9–/D8– (MSB)
CH B8
N – 16
CH B9
N – 16
CH B8
N – 15
CH B9
N – 15
CH B8
N – 14
CH B9
N – 14
CH B8
N – 13
CH B9
N – 13
CH B8
N – 12
09977-004
Figure 4. LVDS Modes for Data Output Timing
SYNC
CLK+
t
HSYNC
t
SSYNC
09977-005
Figure 5. SYNC Input Timing Requirements