Datasheet

3
additional delay on DCO pin’. These settings align the output timing with the input timing
on the capture FPGA.
12. Click the Run button ( ) in VisualAnalog.
13. Adjust the amplitude of the input signal so that the fundamental is at the desired level.
(Examine the “Fund Power” reading in the left panel of the VisualAnalog FFT window.)
14. If desired, click on File>Save Form as in the FFT window to save the FFT plot.