Datasheet

Data Sheet AD9613
Rev. C | Page 15 of 36
Pin No. Mnemonic Type Description
11 B D0−/D1− (LSB) Output Channel B LVDS Output Data 1/Data 0—Complement.
12
B D0+/D1+ (LSB)
Output
Channel B LVDS Output Data 1/Data 0—True.
13 B D2−/D3− Output Channel B LVDS Output Data 3/Data 2—Complement.
14 B D2+/D3+ Output Channel B LVDS Output Data 3/Data 2—True.
15 B D4−/D5− Output Channel B LVDS Output Data 5/Data 4—Complement.
16 B D4+/D5+ Output Channel B LVDS Output Data 5/Data 4—True.
17 B D6−/D7− Output Channel B LVDS Output Data 7/Data 6—Complement.
18 B D6+/D7+ Output Channel B LVDS Output Data 7/Data 6—True.
20 B D8−/D9− Output Channel B LVDS Output Data 9/Data 8—Complement.
21 B D8+/D9+ Output Channel B LVDS Output Data 9/Data 8—True.
22 B D10−/D11− Output Channel B LVDS Output Data 11/Data 10—Complement.
23 B D10+/D11+ Output Channel B LVDS Output Data 11/Data 10—True.
29 A D0−/D1− (LSB) Output Channel A LVDS Output Data 1/Data 0—Complement.
30
A D0+/D1+ (LSB)
Output
Channel A LVDS Output Data 1/Data 0—True.
31 A D2−/D3− Output Channel A LVDS Output Data 3/Data 2—Complement.
32 A D2+/D3+ Output Channel A LVDS Output Data 3/Data 2—True.
33 A D4−/D5− Output Channel A LVDS Output Data 5/Data 4—Complement.
34 A D4+/D5+ Output Channel A LVDS Output Data 5/Data 4—True.
35
A D6−/D7−
Output
Channel A LVDS Output Data 7/Data 6—Complement.
36 A D6+/D7+ Output Channel A LVDS Output Data 7/Data 6—True.
38 A D8−/D9− Output Channel A LVDS Output Data 9/Data 8—Complement.
39 A D8+/D9+ Output Channel A LVDS Output Data 9/Data 8—True.
40 A D10−/D11− Output Channel A LVDS Output Data 11/Data 10—Complement.
41 A D10+/D11+ Output Channel A LVDS Output Data 11/Data 10—True.
43 ORA+ Output Channel A LVDS Overrange Output—True. The overrange indication is
valid on the rising edge of the DCO.
42 ORA− Output Channel A LVDS Overrange Output—Complement. The overrange
indication is valid on the rising edge of the DCO.
25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True.
24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement.
SPI Control
45 SCLK Input SPI Serial Clock.
44 SDIO Input/Output SPI Serial Data I/O.
46 CSB Input SPI Chip Select (Active Low).
Output Enable Bar and
Power-Down
47 OEB Input Output Enable Bar Input (Active Low).
48 PDWN Input Power-Down Input (Active High). Operation depends upon SPI mode;
this input can be configured as power-down or standby. For further
description, refer to Table 14.