Datasheet

AD9613 Data Sheet
Rev. C | Page 34 of 36
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
0x1E User Test
Pattern 3 MSB
(global)
User Test Pattern 3[15:8]
0x00
0x1F User Test
Pattern 4 LSB
(global)
User Test Pattern 4[7:0]
0x00
0x3A Sync control
(global)
Open Open Open Open Open Clock
divider
next sync
only
Clock
divider
sync
enable
Master sync
buffer enable
0x00
1
The channel index register at Address 0x05 should be set to 0x03 (default) when writing to Address 0x00.
MEMORY MAP REGISTER DESCRIPTION
For more information on functions controlled in Register 0x00
to Register 0x20, see the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI.
Sync Control (Register 0x3A)
Bits[7:3]—Reserved
Bit 2—Clock Divider Next Sync Only
If the master sync buffer enable bit (Address 0x3A, Bit 0) and
the clock divider sync enable bit (Address 0x3A, Bit 1) are high,
Bit 2 allows the clock divider to sync to the first sync pulse that
it receives and to ignore the rest. The clock divider sync enable
bit (Address 0x3A, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
enabled when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
Bit 0—Master Sync Buffer Enable
Bit 0 must be set high to enable any of the sync functions. If
the sync capability is not used, this bit should remain low to
conserve power.