Datasheet

AD9613 Data Sheet
Rev. C | Page 6 of 36
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled,
unless otherwise noted.
Table 3.
Parameter Temp Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Internal Common-Mode Bias Full 0.9 V
Differential Input Voltage
Full
0.3
3.6
V p-p
Input Voltage Range
Full
AGND
AVDD
V
Input Common-Mode Range
Full
0.9
1.4
V
High Level Input Current Full 10 22 µA
Low Level Input Current Full −22 −10 µA
Input Capacitance
Full
4
pF
Input Resistance
Full
8
10
12
kΩ
SYNC INPUT
Logic Compliance CMOS/LVDS
Internal Bias Full 0.9 V
Input Voltage Range Full AGND AVDD V
High Level Input Voltage Full 1.2 AVDD V
Low Level Input Voltage Full AGND 0.6 V
High Level Input Current Full −5 +5 µA
Low Level Input Current Full −5 +5 µA
Input Capacitance Full 1 pF
Input Resistance Full 12 16 20 kΩ
LOGIC INPUT (CSB)
1
High Level Input Voltage
Full
1.22
2.1
V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −5 +5 µA
Low Level Input Current Full −80 +45 µA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUT (SCLK)
2
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full 45 70 µA
Low Level Input Current Full −5 +5 µA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUTS (SDIO)
2
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full 45 70 µA
Low Level Input Current Full −5 +5 µA
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF