2-Bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS, 1.
AD9627 TABLE OF CONTENTS Features .............................................................................................. 1 Signal Monitor ................................................................................ 36 Applications ....................................................................................... 1 Peak Detector Mode................................................................... 36 Functional Block Diagram .............................................................
AD9627 REVISION HISTORY 5/10—Rev. A to Rev. B Deleted CP-64-3 Package .................................................. Universal Added CP-64-6 Package .................................................... Universal Changed AD9627BCPZ-80 to AD9267-80 and AD9627BCPZ-105 to AD9627-105 Throughout.......................... 5 Changed AD9627BCPZ-125 to AD9267-125 and AD9627BCPZ-150 to AD9627-150 Throughout.......................... 6 Changes to Figure 6.............................................................
AD9627 GENERAL DESCRIPTION The AD9627 is a dual, 12-bit, 80 MSPS/105 MSPS/125 MSPS/ 150 MSPS analog-to-digital converter (ADC). The AD9627 is designed to support communications applications where low cost, small size, and versatility are desired. exceeds the programmable threshold, the coarse upper threshold indicator goes high. Because this threshold indicator has very low latency, the user can quickly turn down the system gain to avoid an overrange condition.
AD9627 SPECIFICATIONS ADC DC SPECIFICATIONS—AD9627-80/AD9627-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted. Table 1.
AD9627 ADC DC SPECIFICATIONS—AD9627-125/AD9627-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted. Table 2.
AD9627 ADC AC SPECIFICATIONS—AD9627-80/AD9627-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted. Table 3. Parameter1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.3 MHz fIN = 70 MHz fIN = 140 MHz fIN = 220 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.
AD9627 ADC AC SPECIFICATIONS—AD9627-125/AD9627-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted. Table 4. Parameter1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.3 MHz fIN = 70 MHz fIN = 140 MHz fIN = 220 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.
AD9627 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 5.
AD9627 Parameter Input Resistance Input Capacitance DIGITAL OUTPUTS CMOS Mode—DRVDD = 3.3 V High Level Output Voltage IOH = 50 μA IOH = 0.5 mA Low Level Output Voltage IOL = 1.6 mA IOL = 50 μA CMOS Mode—DRVDD = 1.8 V High Level Output Voltage IOH = 50 μA IOH = 0.5 mA Low Level Output Voltage IOL = 1.6 mA IOL = 50 μA LVDS Mode—DRVDD = 1.
AD9627 SWITCHING SPECIFICATIONS—AD9627-80/AD9627-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 6.
AD9627 SWITCHING SPECIFICATIONS—AD9627-125/AD9627-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 7.
AD9627 TIMING SPECIFICATIONS Table 8. Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO Conditions Min Typ SYNC to rising edge of CLK setup time SYNC to rising edge of CLK hold time tDIS_SDIO SPORT TIMING REQUIREMENTS tCSSCLK tSSCLKSDO tSSCLKSDFS Max 0.24 0.
AD9627 N+1 N+2 N+3 N N+4 N+8 tA N+5 N+6 N+7 tCLK CLK+ CLK– tPD CH A/CH B DATA A CH A/CH B FAST DETECT A B N – 13 B N–7 A B N – 12 A B N – 11 B N–6 A A B N–5 A B N – 10 A B N–4 A B N–9 A B N–3 A B A N–8 A N–7 B A N–2 tDCO B B N–1 A B A N–6 A B B N–5 A N B N+1 A N–4 A N+2 tCLK 06571-003 DCO+ DCO– Figure 3.
AD9627 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 9.
AD9627 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DRGND D3B D2B D1B D0B (LSB) DNC DNC DVDD FD3B FD2B FD1B FD0B SYNC CSB CLK– CLK+ PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD9627 PARALLEL CMOS TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCLK/DFS SDIO/DCS AVDD AVDD VIN+B VIN–B RBIAS CML SENSE VREF VIN–A VIN+A AVDD SMI SDFS SMI SCLK/PDWN SMI SDO/OEB NOTES 1.
AD9627 Pin No. Mnemonic Digital Input 52 SYNC Digital Outputs 14 D0A (LSB) 15 D1A 16 D2A 17 D3A 18 D4A 19 D5A 22 D6A 23 D7A 25 D8A 26 D9A 27 D10A 28 D11A (MSB) 60 D0B (LSB) 61 D1B 62 D2B 63 D3B 2 D4B 3 D5B 4 D6B 5 D7B 6 D8B 7 D9B 8 D10B 9 D11B (MSB) 11 DCOA 10 DCOB SPI Control 48 SCLK/DFS 47 SDIO/DCS 51 CSB Signal Monitor Port 33 SMI SDO/OEB 35 SMI SDFS 34 SMI SCLK/PDWN Type Description Input Digital Synchronization Pin. Slave mode only.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DRGND DNC DNC FD3+ FD3– FD2+ FD2– DVDD FD1+ FD1– FD0+ FD0– SYNC CSB CLK– CLK+ AD9627 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD9627 PARALLEL LVDS TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCLK/DFS SDIO/DCS AVDD AVDD VIN+B VIN–B RBIAS CML SENSE VREF VIN–A VIN+A AVDD SMI SDFS SMI SCLK/PDWN SMI SDO/OEB NOTES 1. DNC = DO NOT CONNECT. 2.
AD9627 Pin No.
AD9627 EQUIVALENT CIRCUITS 1kΩ SCLK/DFS 26kΩ 06571-008 06571-012 VIN Figure 8. Equivalent Analog Input Circuit Figure 12. Equivalent SCLK/DFS Input Circuit AVDD 1kΩ 1.2V 10kΩ SENSE 10kΩ CLK+ 06571-009 06571-013 CLK– Figure 13. Equivalent SENSE Circuit Figure 9. Equivalent Clock Input Circuit DRVDD AVDD 26kΩ 1kΩ 06571-010 06571-014 CSB DRGND Figure 10. Digital Output Figure 14.
AD9627 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, sample rate = 150 MSPS, DCS enabled, 1.0 V internal reference, 2 V p-p differential input, VIN = −1.0 dBFS, and 64k sample, TA = 25°C, unless otherwise noted. 0 0 150MSPS 2.3MHz @ –1dBFS SNR = 69.4dBc (70.4dBFS) ENOB = 11.4 BITS SFDR = 86.
AD9627 0 0 150MSPS 440MHz @ –1dBFS SNR = 65.7dBc (66.7dBFS) ENOB = 10.4 BITS SFDR = 70.0dBc –20 AMPLITUDE (dBFS) –40 SECOND HARMONIC –60 THIRD HARMONIC –80 10 20 30 40 50 60 70 THIRD HARMONIC FREQUENCY (MHz) –120 06571-022 0 0 10 20 30 40 50 60 FREQUENCY (MHz) Figure 25. AD9627-125 Single-Tone FFT with fIN = 70 MHz Figure 22. AD9627-150 Single-Tone FFT with fIN = 440 MHz 0 0 125MSPS 2.3MHz @ –1dBFS SNR = 69.5dBc (70.5dBFS) ENOB = 11.4 BITS SFDR = 86.
AD9627 120 95 SFDR = +85°C SFDR (dBFS) 90 85 80 SFDR = +25°C SNR/SFDR (dBc) SNR (dBFS) 60 40 80 SFDR = –40°C 75 70 SFDR (dBc) 65 85dB REFERENCE LINE SNR = +25°C SNR = +85°C SNR = –40°C 20 60 SNR (dBc) –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) 55 06571-028 0 –90 0 50 100 150 200 250 300 350 400 450 INPUT FREQUENCY (MHz) Figure 28. AD9627-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 2.
AD9627 0 0 –20 SFDR (dBc) AMPLITUDE (dBFS) SFDR/IMD3 (dBc AND dBFS) –20 150MSPS 169.1MHz @ –7dBFS 172.1MHz @ –7dBFS SFDR = 83.8dBc (90.8dBFS) –40 IMD3 (dBc) –60 –80 –40 –60 –80 SFDR (dBFS) –100 –100 IMD3 (dBFS) –66 –54 –42 –30 –18 –6 INPUT AMPLITUDE (dBFS) –120 0 30 40 50 60 70 Figure 37. AD9627-150 Two-Tone FFT with fIN1 = 169.1 MHz and fIN2 = 172.1 MHz 0 0 NPR = 61.5dBc NOTCH @ 18.
AD9627 12 100 0.3 LSB rms 95 90 8 SNR/SFDR (dBc) NUMBER OF HITS (1M) 10 6 4 SFDR DCS ON 85 80 SFDR DCS OFF 75 SNR DCS ON 70 2 65 N–2 N–1 N N+1 N+2 N+3 OUTPUT CODE 06571-040 N–3 60 20 60 80 DUTY CYCLE (%) Figure 40. AD9627 Grounded Input Histogram Figure 43. AD9627-150 SNR/SFDR vs. Duty Cycle with fIN = 10.3 MHz 0.4 95 0.3 90 0.2 SFDR 85 SNR/SFDR (dBc) INL ERROR (LSB) 40 06571-043 SNR DCS OFF 0 0.1 0 –0.1 80 75 70 –0.
AD9627 THEORY OF OPERATION The AD9627 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any fS/2 frequency segment from dc to 200 MHz, using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance.
AD9627 An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver. An example is shown in Figure 50. See the AD8352 data sheet for more information. The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD9627 (see Figure 46), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 499Ω 1V p-p R 49.
AD9627 A stable and accurate voltage reference is built into the AD9627. The input range can be adjusted by varying the reference voltage applied to the AD9627, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are summarized in the sections that follow. The Reference Decoupling section describes the best practices PCB layout of the reference.
AD9627 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 54 shows the typical drift characteristics of the internal reference in 1.0 V mode. 2.5 This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9627 while preserving the fast rise and fall times of the signal that are critical to a low jitter performance. 2.0 1.5 1.0 0.5 0 –0.
AD9627 In some applications, it may be acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, the CLK+ pin should be driven directly from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 60). CLK+ can be driven directly from a CMOS gate. Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages of up to 3.
AD9627 1.00 The maximum DRVDD current (IDRVDD) can be calculated as IDRVDD = VDRVDD × CLOAD × fCLK × N IAVDD 0.75 TOTAL POWER (W) As shown in Figure 63 through Figure 66, the power dissipated by the AD9627 is proportional to its sample rate. In CMOS output mode, the digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. 0.4 TOTAL POWER 0.50 0.1 IDRVDD IDVDD IAVDD IDRVDD 0 50 75 100 125 0 150 SAMPLE RATE (MSPS) 1.25 1.
AD9627 DIGITAL OUTPUTS Digital Output Enable Function (OEB) The AD9627 output drivers can be configured to interface with 1.8 V to 3.3 V CMOS logic families by matching DRVDD to the digital supply of the interfaced logic. The AD9627 can also be configured for LVDS outputs using a DRVDD supply voltage of 1.8 V. The AD9627 has a flexible three-state ability for the digital output pins. The three-state mode is enabled using the SMI SDO/OEB pin or through the SPI interface.
AD9627 ADC OVERRANGE AND GAIN CONTROL In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overflow indicator provides after-the-fact information on the state of the analog input that is of limited usefulness. Therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs.
AD9627 When the fast detect mode select bits are set to 0b001, 0b010, or 0b011, a subset of the fast detect output pins is available. In these modes, the fast detect output pins have a latency of six clock cycles. Table 19 shows the corresponding ADC input levels when the fast detect mode select bits are set to 0b001 (that is, when ADC fast magnitude is presented on the FD[3:1] pins). Table 19.
AD9627 Increment Gain (IG) and Decrement Gain (DG) with the magnitude at the output of the ADC. This comparison is subject to the ADC clock latency but allows a finer, more accurate comparison. The fine upper threshold magnitude is defined by the following equation: The increment gain and decrement gain indicators are intended to be used together to provide information to enable external gain control.
AD9627 SIGNAL MONITOR The signal monitor result values can be obtained from the part by reading back internal registers at Address 0x116 to Address 0x11B, using the SPI port or the signal monitor SPORT output. The output contents of the SPI-accessible signal monitor registers are set via the two signal monitor mode bits of the signal monitor control register. Both ADC channels must be configured for the same signal monitor mode.
AD9627 Figure 69 illustrates the rms magnitude monitoring logic. DOWN COUNTER IS COUNT = 1? LOAD CLEAR ACCUMULATOR TO MEMORY SIGNAL MONITOR MAP/SPORT HOLDING REGISTER (SMR) LOAD 06571-069 FROM INPUT PORTS Figure 69. ADC Input RMS Magnitude Monitoring Block Diagram For rms magnitude mode, the value in the signal monitoring result (SMR) register is a 20-bit fixed-point number. The following equation can be used to determine the rms magnitude in dBFS from the MAG value in the register.
AD9627 DC Correction Bandwidth SIGNAL MONITOR SPORT OUTPUT The dc correction circuit is a high-pass filter with a programmable bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS). The bandwidth is controlled by writing the 4-bit dc correction register located at Register 0x10C, Bits[5:2].
AD9627 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9627 includes built-in test features designed to enable verification of the integrity of each channel as well as facilitate board level debugging. A BIST (built-in self-test) feature is included that verifies the integrity of the digital datapath of the AD9627. Various output test options are also provided to place predictable values on the outputs of the AD9627.
AD9627 CHANNEL/CHIP SYNCHRONIZATION The AD9627 has a SYNC input that offers the user flexible synchronization options for synchronizing the internal blocks. The clock divider sync feature is useful for guaranteeing synchronized sample clocks across multiple ADCs. The signal monitor block can also be synchronized using the SYNC input, allowing properties of the input signal to be measured during a specific time period.
AD9627 SERIAL PORT INTERFACE (SPI) The AD9627 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port.
AD9627 CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES In applications that do not interface to the SPI control registers, the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin, and the SMI SCLK/PDWN pin serve as standalone CMOScompatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer, output data format, output enable, and power-down feature control.
AD9627 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Logic Levels Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the channel index and transfer registers (Address 0x05 and Address 0xFF); the ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x25); and the digital feature control registers (Address 0x100 to Address 0x11B).
AD9627 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 25 are not currently supported for this device. Table 25.
AD9627 Addr (Hex) 0x0E 0x10 0x14 Register Name BIST Enable (Local) Offset Adjust (Local) Output Mode Bit 7 (MSB) Open Bit 6 Open Open Open Drive strength 0 V to 3.3 V CMOS or ANSI LVDS; 1 V to 1.8 V CMOS or reduced LVDS (global) Invert DCO clock Output type 0 = CMOS 1 = LVDS (global) Open Output enable bar (local) Open Open Open Open Open 0x16 Clock Phase Control (Global) 0x17 DCO Output Delay (Global) Open 0x18 VREF Select (Global) Reference voltage selection 00 = 1.25 V p-p 01 = 1.
AD9627 Addr (Hex) 0x109 0x10A 0x10B 0x10C 0x10D 0x10E 0x10F 0x110 0x111 Register Name Fine Lower Threshold Register 1 (Local) Increase Gain Dwell Time Register 0 (Local) Increase Gain Dwell Time Register 1 (Local) Signal Monitor DC Correction Control (Global) Signal Monitor DC Value Channel A Register 0 (Global) Signal Monitor DC Value Channel A Register 1 (Global) Signal Monitor DC Value Channel B Register 0 (Global) Signal Monitor DC Value Channel B Register 1 (Global) Signal Monitor SPORT Contro
AD9627 Addr (Hex) 0x117 0x118 0x119 0x11A 0x11B Register Name Signal Monitor Result Channel A Register 1 (Global) Signal Monitor Result Channel A Register 2 (Global) Signal Monitor Result Channel B Register 0 (Global) Signal Monitor Result Channel B Register 1 (Global) Signal Monitor Result Channel B Register 2 (Global) Bit 7 (MSB) Bit 6 Bit 5 Open Open Open Open Open Bit 4 Bit 3 Bit 2 Signal Monitor Result Channel A[15:8] Open Bit 1 Bit 0 (LSB) Default Value (Hex) Signal Monitor Value Ch
AD9627 Increase Gain Dwell Time (Register 0x10A and Register 0x10B) Register 0x10A, Bits[7:0]—Increase Gain Dwell Time[7:0] Register 0x10B, Bits[7:0]—Increase Gain Dwell Time[15:8] These registers are programmed with the dwell time in ADC clock cycles for which the signal must be below the fine lower threshold value before the increase gain output is asserted.
AD9627 Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x113, Bits[7:0]—Signal Monitor Period[7:0] Register 0x114, Bits[7:0]—Signal Monitor Period[15:8] Register 0x115, Bits[7:0]—Signal Monitor Period[23:16] This 24-bit value sets the number of clock cycles over which the signal monitor performs its operation. The minimum value for this register is 128 cycles; programmed values less than 128 revert to 128.
AD9627 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9627 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and Ground Recommendations When connecting power to the AD9627, it is recommended that two separate 1.
AD9627 EVALUATION BOARD The AD9627 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially through a double balun configuration (default) or optionally through the AD8352 differential driver. The ADC can also be driven in a single-ended fashion. Separate power pins are provided to isolate the DUT from the AD8352 drive circuitry.
AD9627 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9627 evaluation board. POWER Connect the switching power supply that is provided in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P500. VIN The evaluation board is set up for a double balun configuration analog input with optimum 50 Ω impedance matching from 70 MHz to 200 MHz.
AD9627 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION 1. Remove C1, C17, C18, and C117 in the default analog input path. This section provides a brief description of the alternative analog input drive configuration using the AD8352. When using this particular drive option, some additional components need to be populated. For more details on the AD8352 differential driver, including how it works and its optional pin settings, consult the AD8352 data sheet. 2. Populate C8 and C9 with 0.
AIN+ AIN- S1 2 S2 1 R28 1 0 OHM R121 RES0402 0 OHM R120 57.6 OHM R1 57.6 OHM INA+ 0.1U C117 0.1U C1 R2 INA+ 0 OHM 0.1U C47 INA- 0.1U C9 T10 0 OHM R54 P 3 S 2 1 DNP R36 5 4 5 4 S ETC1-1-13 P T1 1 2 3 1ADT1_1W 6T 2 3 T7 0 OHM R110 CML 1 2 3 P ETC1-1-13 S T2 5 4 0.1U C18 0.1U C17 DEFAULT AMPLIFIER INPUT PAT H 4 5 ETC1-1-13 F 0.1U R31 R29 R35 0 OHM 24.9 OHM 24.9 OHM C8 4.12K 0.1U C11 0.
Figure 76. Evaluation Board Schematic, Channel B Analog Inputs AIN+ AIN- S4 S3 1 1 57.6 OHM R52 57.6 OHM R51 0 OHM RES0402 R123 0 OHM RES0402 R122 INB0.1U C31 INB+ 0.1U C6 0.1U C28 0 OHM R67 INB- 4 5 S 3 2 1 DNP 0.1U 0.1U C39 .3PF C128 0.1U 4 5 T8 4 5 6 P T3 S ETC1-1-13 3 2 1 3 2 1 ADT1_1WT 0 OHM R111 CML 4 5 P T4 S ETC1-1-13 3 2 1 0 OHM R132 DNP R133 0 OHM R6 DEFAULT AMPLIFIER INPUT PAT H 0 OHM R55 T11 C51 P ETC1-1-13 0 OHM F 0.
S6 SMA200U P ENC\ ENC S5 1 1 R30 R7 R8 57.6 OHM 57.6 OHM SMA200U P 2 2 0 OHM 10K OHM 10K OHM R85 R82 0 OHM R3 0 OHM R90 Figure 77. Evaluation Board Schematic, DUT Clock Input 0.001U C77 0.001U C94 0.001U C63 0.001U 4 5 0.1U OPT_CLK- 3 S 2 T5 ETC1-1-13 P 1 6 T9 5 4 ADT1_1WT 1 2 3 C56 0.001U C79 0 OHM R33 0 OHM R32 0.001U C78 OPT_CLK- ALTCLK- OPT_CLK+ ALTCLK+ 0 OHM R79 0 OHM R101 0 OHM R99 0 OHM R78 R83 0.1U C21 24.9 OHM R84 0.1U C20 24.
1 S7 RES040 2 0 OHM R12 5 RES040 2 VS_OUT_DR C10 1 0.1U C10 0 0.1U 0 OHM R12 4 R1 0 0 OHM VCXO_CLK + 0.1U C10 4 VCXO_CLK - 1 CLK IN AD9516 LD 49.9 OHM TES T 2 0.1U C9 8 0.1U C14 3 0.1U C14 2 18PF C8 0 0.1U C99 VS SCL K VCP BYPASS_LD O 9 LF CLKB NC1 SCL K 14 15 16 0.1U 0.
CP Figure 79. Evaluation Board Schematic, Optional AD9516 Loop Filter/VCO and SYNC Input BYPASS_LDO VAL R136 SYNC S12 SMA200U P 2 1 R45 R98 VAL C90 SEL RES060 3 57.6 OH M C89 SEL R93 VAL VAL R137 SEL C91 C144 SEL LD Charge Pump Filter 0.1U C25 VAL R97 3 2 A2 GND A1 NL27WZ0 C92 SEL 4 Y1 Y2 VCC 0 OH M R116 RES040 2 0 OH M R117 RES040 2 4 5 6 RES040 2 LF TP1 1 R87 OSCVECTRON_VS500 RES040 2 0 OH M R104 U25 4 OUT2 3 GND 6 VCC 5 OUT1 24.
Rev. B | Page 59 of 76 Figure 80. Evaluation Board Schematic, DUT NC D7A NC DVDD2 FD3B FD2B D11A_MSB_ FD1B FD0B FD0A FD1A SYNC FD2A SPI_CSB CLK- FD3A CLK+ 57 52 51 50 49 C137 0.001U D0B_LSB U1 SPI_SCLK/DFS D6A C121 0.1U C120 0.1U RES040 2 SPI_SDIO/DCS AVDD3 D1B C109 0.1U C40 0.1U 48 47 46 AVDD2 VIN+B DRVDD1 C122 0.001U C126 0.001U SPI_SCL K SPI_SDI O AVDD 45 44 DRGND1 C127 0.001U R64 0 OH M AVDD VIN+ B 43 VIN-B RBIAS AD9627 0.
D5A D4A Figure 81.
Figure 82. Evaluation Board Schematic, SPI Circuitry Rev. B | Page 61 of 76 SDO SDI CSB SCLK CSB_2 R65 CSB SCLK V_DIG RES0402 10K OHM C13 0.1U 3 2 1 A2 A2 Y2 VCC Y1 4 5 6 Y1 4 5 6 V_DIG V_DIG C81 0.
1 3 SMDC110F C41 10U Figure 83. Evaluation Board Schematic, Power Supply Rev. B | Page 62 of 76 P4 P3 P2 P1 VCP VS DRVDDIN SJ35 P4 6 P6 5 P5 4 P4 P33 2 P2 P3 P11 1 1 AVDDIN CR7 OPTIONAL POWER SUPPLY INPUT S POWER_JACK F2 2 1 2 L6 IND1210 10UH 10uh L10 IND1210 L9 IND1210 10UH 1 2 2 2 BNX- 016 3 PSG 1 BIAS C53 10U C102 10U C52 10U C58 0.1U C103 0.1U C57 0.
PWR_IN PWR_IN Figure 84. Evaluation Board Schematic, Power Supply (Continued) Rev. B | Page 63 of 76 VC P SD 6 PA D ADP333 9 VC P 5 C12 4 10 U 10 U VS_OUT_DR C11 9 GN D OUT 1 OUT2 2 FB 3 VR2 OU T OU T Power Supply ByPass Capacitors 1U C13 2 8 IN 7 IN2 ADP3334 1U IN VR 6 C13 5 3 1U C13 3 PA D ADP333 9 4 GN D 1 4 GN D 1 IN VS 1U C13 6 1U C13 4 10 U C11 8 R2 5 R1 5 VR 5 140 KOH M 0.001 U C9 5 SJ36 78.
AD9627 06571-085 EVALUATION BOARD LAYOUTS Figure 85. Evaluation Board Layout, Primary Side Rev.
06571-086 AD9627 Figure 86. Evaluation Board Layout, Ground Plane Rev.
06571-087 AD9627 Figure 87. Evaluation Board Layout, Power Plane Rev.
06571-088 AD9627 Figure 88. Evaluation Board Layout, Power Plane Rev.
06571-089 AD9627 Figure 89. Evaluation Board Layout, Ground Plane Rev.
06571-090 AD9627 Figure 90. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev.
06571-091 AD9627 Figure 91. Evaluation Board Layout, Silkscreen, Primary Side Rev.
06571-092 AD9627 Figure 92. Evaluation Board Layout, Silkscreen, Secondary Side Rev.
AD9627 BILL OF MATERIALS Table 26. Evaluation Board Bill of Materials (BOM)1, 2 Item 1 2 Qty 1 55 3 1 Reference Designator AD9627CE_REVB C1 to C3, C6, C7, C13, C14, C17, C18, C20 to C26, C32, C57 to C61, C65 to C76, C81 to C83, C96 to C101, C103, C105, C107, C108, C110 to C116, C145 C80 4 2 C5, C84 5 10 6 13 7 10 8 1 C33, C35, C63, C93 to C95, C122, C126, C127, C137 C15, C42 to C45, C129 to C136 C27, C41, C52 to C54, C62, C102, C118, C119, C124 CR5 9 2 CR6, CR9 Description PCB 0.
AD9627 Item 26 Qty 1 Reference Designator R16 27 3 R17, R22, R23 28 7 29 3 R18, R24, R63, R65, R82, R118, R140 R19, R20, R21 30 9 31 5 R26, R27, R43, R46, R47, R70, R71, R73, R74 R57, R59 to R62 32 1 R58 33 1 R76 34 4 S2, S3, S5 ,S12 Description 261 Ω, 0603, 1/10 W, 1% resistor 100 kΩ, 0603, 1/10 W, 1% resistor 10 kΩ, 0402, 1/16 W, 1% resistor 1 kΩ, 0603, 1/10 W, 1% resistor 33 Ω, 0402, 1/16 W, 5% resistor Package R0603 Manufacturer NIC Components Mfg.
AD9627 OUTLINE DIMENSIONS 0.60 MAX 9.00 BSC SQ 0.60 MAX 64 1 49 PIN 1 INDICATOR 48 PIN 1 INDICATOR 8.75 BSC SQ 0.50 BSC 0.50 0.40 0.30 0.22 MIN 7.50 REF 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 02-23-2010-B 0.80 MAX 0.65 TYP 12° MAX 16 17 33 32 TOP VIEW 1.00 0.85 0.80 7.55 7.50 SQ 7.
AD9627 NOTES Rev.
AD9627 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06571-0-5/10(B) Rev.
