Datasheet

AD9627
Rev. B | Page 11 of 76
SWITCHING SPECIFICATIONS—AD9627-80/AD9627-105
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and
DCS enabled, unless otherwise noted.
Table 6.
Parameter Temperature
AD9627-80 AD9627-105
Unit Min Typ Max Min Typ Max
CLOCK INPUT PARAMETERS
Input Clock Rate Full 625 625 MHz
Conversion Rate
DCS Enabled
1
Full 20 80 20 105 MSPS
DCS Disabled
1
Full 10 80 10 105 MSPS
CLK Period—Divide-by-1 Mode (t
CLK
) Full 12.5 9.5 ns
CLK Pulse Width High
Divide-by-1 Mode, DCS Enabled Full 3.75 6.25 8.75 2.85 4.75 6.65 ns
Divide by-1-Mode, DCS Disabled Full 5.63 6.25 6.88 4.28 4.75 5.23 ns
Divide-by-2 Mode, DCS Enabled Full 1.6 1.6 ns
Divide-by-3 Through Divide-by-8
Modes, DCS Enabled
Full 0.8 0.8 ns
DATA OUTPUT PARAMETERS (DATA, FD)
CMOS Mode—DRVDD = 3.3 V
Data Propagation Delay (t
PD
)
2
Full 2.2 4.5 6.4 2.2 4.5 6.4 ns
DCO Propagation Delay (t
DCO
) Full 3.8 5.0 6.8 3.8 5.0 6.8 ns
Setup Time (t
S
) Full 6.25 5.25 ns
Hold Time (t
H
) Full 5.75 4.25 ns
CMOS Mode—DRVDD = 1.8 V
Data Propagation Delay (t
PD
)
2
Full 2.4 5.2 6.9 2.4 5.2 6.9 ns
DCO Propagation Delay (t
DCO
) Full 4.0 5.6 7.3 4.0 5.6 7.3 ns
Setup Time (t
S
) Full 6.65 5.15 ns
Hold Time (t
H
) Full 5.85 4.35 ns
LVDS Mode—DRVDD = 1.8 V
Data Propagation Delay (t
PD
)
2
Full 2.0 4.8 6.3 2.0 4.8 6.3 ns
DCO Propagation Delay (t
DCO
) Full 5.2 7.3 9.0 5.2 7.3 9.0 ns
CMOS Mode Pipeline Delay (Latency) Full 12 12 Cycles
LVDS Mode Pipeline Delay (Latency)
Channel A/Channel B
Full 12/12.5 12/12.5 Cycles
Aperture Delay (t
A
) Full 1.0 1.0 ns
Aperture Uncertainty (Jitter, t
J
) Full 0.1 0.1 ps rms
Wake-Up Time
3
Full 350 350 μs
OUT-OF-RANGE RECOVERY TIME Full 2 2 Cycles
1
Conversion rate is the clock rate after the divider.
2
Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
3
Wake-up time is dependent on the value of the decoupling capacitors.