Datasheet

AD9627
Rev. B | Page 14 of 76
CLK+
DCO+
DCO–
C
H A/CH B DAT
A
N
N+ 1
N+2
N+ 3
N+ 4
N+ 5
N+ 6
N+ 7
N+ 8
N – 12 N – 11 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4
N – 13
CLK–
t
CLK
t
PD
t
DCO
t
CLK
t
A
CH A/CH B FAST
DETECT
ABABABABABABABABA AB
N – 10
N – 6 N – 5 N – 3 N – 2 N – 1 N N + 1 N + 2N – 7
ABABABABABABABABA AB
N – 4
06571-003
Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 001 Through Fast Detect Mode Select Bits = 100)
SYNC
CLK+
t
HSYNC
t
SSYNC
06571-004
Figure 4. SYNC Input Timing Requirements
CLK+
SMI SCLK
SMI SDFS
DATA DATASMI SDO
CLK–
t
CSSCLK
t
SSCLKSDFS
t
SSCLKSDO
06571-005
Figure 5. Signal Monitor SPORT Output Timing (Divide-by-2 Mode)