Datasheet
AD9627
Rev. B | Page 18 of 76
0
6571-007
PIN 1
INDICATOR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D5+
D6–
D6+
DRGND
DRVDD
D7–
D7+
DVDD
D8–
D8+
D9–
D9+
D10–
D10+
D11– (MSB)
D11+ (MSB)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DRGND
DNC
DNC
FD3+
FD3–
FD2+
FD2–
DVDD
FD1+
FD1–
FD0+
FD0–
SYNC
CSB
CLK–
CLK+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DRVDD
DNC
DNC
D0– (LSB)
D0+ (LSB)
D1–
D1+
D2–
D2+
DCO–
DCO+
D3–
D3+
D4–
D4+
D5–
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN+B
VIN–B
RBIAS
CML
SENSE
VREF
VIN–A
VIN+A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9627
PARALLEL LVDS
TOP VIEW
(Not to Scale)
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.
Figure 7. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
Table 12. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No. Mnemonic Type Description
ADC Power Supplies
20, 64 DRGND Ground Digital Output Ground.
1, 21 DRVDD Supply Digital Output Driver Supply (1.8 V to 3.3 V).
24, 57 DVDD Supply Digital Power Supply (1.8 V Nominal).
36, 45, 46 AVDD Supply Analog Power Supply (1.8 V Nominal).
0 AGND Ground Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
2, 3, 62,
63
DNC Do Not Connect.
ADC Analog
37 VIN+A Input Differential Analog Input Pin (+) for Channel A.
38 VIN−A Input Differential Analog Input Pin (−) for Channel A.
44 VIN+B Input Differential Analog Input Pin (+) for Channel B.
43 VIN−B Input Differential Analog Input Pin (−) for Channel B.
39 VREF Input/Output Voltage Reference Input/Output.
40 SENSE Input Voltage Reference Mode Select. See Table 14 for details.
42 RBIAS Input/Output External Reference Bias Resistor.
41 CML Output Common-Mode Level Bias Output for Analog Inputs.
49 CLK+ Input ADC Clock Input—True.
50 CLK− Input ADC Clock Input—Complement.
ADC Fast Detect Outputs
54 FD0+ Output Channel A/Channel B LVDS Fast Detect Indicator 0—True. See Table 17 for details.
53 FD0− Output Channel A/Channel B LVDS Fast Detect Indicator 0—Complement. See Table 17 for details.
56 FD1+ Output Channel A/Channel B LVDS Fast Detect Indicator 1—True. See Table 17 for details.
55 FD1− Output Channel A/Channel B LVDS Fast Detect Indicator 1—Complement. See Table 17 for details.
59 FD2+ Output Channel A/Channel B LVDS Fast Detect Indicator 2—True. See Table 17 for details.
58 FD2− Output Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 17 for details.
61 FD3+ Output Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 17 for details.
60 FD3− Output Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 17 for details.
Digital Input
52 SYNC Input Digital Synchronization Pin. Slave mode only.