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AD9627
Rev. B | Page 19 of 76
Pin No. Mnemonic Type Description
Digital Outputs
5 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True.
4 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement.
7 D1+ Output Channel A/Channel B LVDS Output Data 1—True.
6 D1− Output Channel A/Channel B LVDS Output Data 1—Complement.
9 D2+ Output Channel A/Channel B LVDS Output Data 2—True.
8 D2− Output Channel A/Channel B LVDS Output Data 2—Complement.
13 D3+ Output Channel A/Channel B LVDS Output Data 3—True.
12 D3− Output Channel A/Channel B LVDS Output Data 3—Complement.
15 D4+ Output Channel A/Channel B LVDS Output Data 4 —True.
14 D4− Output Channel A/Channel B LVDS Output Data 4—Complement.
17 D5+ Output Channel A/Channel B LVDS Output Data 5—True.
16 D5− Output Channel A/Channel B LVDS Output Data 5—Complement.
19 D6+ Output Channel A/Channel B LVDS Output Data 6—True.
18 D6− Output Channel A/Channel B LVDS Output Data 6—Complement.
23 D7+ Output Channel A/Channel B LVDS Output Data 7—True.
22 D7− Output Channel A/Channel B LVDS Output Data 7—Complement.
26 D8+ Output Channel A/Channel B LVDS Output Data 8—True.
25 D8− Output Channel A/Channel B LVDS Output Data 8—Complement.
28 D9+ Output Channel A/Channel B LVDS Output Data 9—True.
27 D9− Output Channel A/Channel B LVDS Output Data 9—Complement.
30 D10+ Output Channel A/Channel B LVDS Output Data 10—True.
29 D10− Output Channel A/Channel B LVDS Output Data 10—Complement.
32 D11+ (MSB) Output Channel A/Channel B LVDS Output Data 11—True.
31 D11− (MSB) Output Channel A/Channel B LVDS Output Data 11—Complement.
11 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True.
10 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement.
SPI Control
48 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode.
47 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
51 CSB Input SPI Chip Select (Active Low).
Signal Monitor Port
33 SMI SDO/OEB Input/Output Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode.
35 SMI SDFS Output Signal Monitor Serial Data Frame Sync.
34 SMI SCLK/PDWN Input/Output Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.