Datasheet

AD9627
Rev. B | Page 49 of 76
Signal Monitor Period (Register 0x113 to Register 0x115)
Register 0x113, Bits[7:0]—Signal Monitor Period[7:0]
Register 0x114, Bits[7:0]—Signal Monitor Period[15:8]
Register 0x115, Bits[7:0]—Signal Monitor Period[23:16]
This 24-bit value sets the number of clock cycles over which the
signal monitor performs its operation. The minimum value for
this register is 128 cycles; programmed values less than 128 revert
to 128.
Signal Monitor Result Channel A (Register 0x116 to
Register 0x118)
Register 0x116, Bits[7:0]—Signal Monitor Result
Channel A[7:0]
Register 0x117, Bits[7:0]—Signal Monitor Result
Channel A[15:8]
Register 0x118, Bits[7:4]—Reserved
Register 0x118, Bits[3:0]—Signal Monitor Result
Channel A[19:16]
This 20-bit value contains the result calculated by the signal
monitoring block for Channel A. The result is dependent on the
settings in Register 0x112[2:1].
Signal Monitor Result Channel B (Register 0x119 to
Register 0x11B)
Register 0x119, Bits[7:0]— Signal Monitor Result
Channel B[7:0]
Register 0x11A, Bits[7:0]—Signal Monitor Result
Channel B[15:8]
Register 0x11B, Bits[7:4]—Reserved
Register 0x11B, Bits[3:0]—Signal Monitor Result
Channel B[19:16]
This 20-bit value contains the result calculated by the signal
monitoring block for Channel B. The result is dependent on the
settings in Register 0x112[2:1].