Datasheet

AD9627
Rev. B | Page 57 of 76
06571-078
TES T
TEST
TEST
BYPASS_LD O CLK CP
CP_RSET
GND_ES D
GND_OUT89_DI V
GND_REF
LD LF NC1
NC2
NC3
NC4
OUT0
OUT1
OUT 2 OUT 3
OUT4
OUT5
OUT 6 OUT 7 OUT 8 OUT 9
REFIN
REFMO N REF_SE L
RSET_CLOCK
SCL K
SDIO
SDO
STATU S VCP VS_CLK_DIS T
VS_OUT01_DI V
VS_OUT01_DRV
VS_OUT23_DI V
VS_OUT23_DR V
VS_OUT45_DI V
VS_OUT45_DRV
VS_OUT67_ 1
VS_OUT67_ 2
VS_OUT89_ 1
VS_OUT89_ 2
VS_PLL_ 1
VS_PLL_2
VS_PRESCALER
VS_REF
VS_VC O CLK B
CSB
OUT0B
OUT1B
OUT2 B OUT3 B
OUT4B
OUT5B
OUT6 B OUT7 B OUT8 B OUT9 B
PDB
REFINB
RESETB
SYNC B
AD9516_64LFCS P
PAD
2
AD9516 CLK IN
LVDS
OUTPUT
LVPECL OUTPUT
TO ADC LVPECL
1
S7
VCXO_CLK -
R89
49.9 OHM
R12
4.12K
R9
100 OHM
R75
100 OHM
1
TP8
2
1
S11
OUT6 P OUT6 N
10 13
5
62
44 37
59
3 9
15
18
19
20
56
53
43 40
25
28
48 46 33 35
2 7
58
22
21
6 4
12
51
54
38 41
30
27
49
5031
32
61
60
57
11 14
17
55
52
42 39
26
29
47 45 34 36
24
63
23
8 1
16
64
U2
200 R91
200 R86
R11
5.1K
200 R88
200 R92R12 5
RES040 2
0OHM
R12 4
RES040 2
0OHM
R10
0OHM
C10 4 0.1U
C10 1 0.1U
C98 0.1U
C99 0.1U
C96 0.1U
C97 0.1U
C10 0 0.1U
SYN C
VCP
VS_OUT_DR
VCXO_CLK +
1
TP18
LD
1
TP19
C80 18PF
C14 1
0.001U
C86
0.1U
C85
0.1U
C87
0.1U
C88
0.1U
C14 3
0.1U
C14 2
0.1U
2
1
S10
2
1
S9
2
1
S8
1
T
P20
OPT_CLK+
SCL K
VS
SYNC B
RESETB
OPT_CLK-
PDB
CSB_2
VS
VS
VS
VS
VS
VS_OUT_DR
VS_OUT_D R
VS
VS_OUT_D R
VCP
SDO
SDI
REF_SE L
LF
AGN D
AGN D
AGN DCP
BYPASS_LD O
STATU S
REFMO N
ALTCLK - ALTCLK +
Figure 78. Evaluation Board Schematic, Optional AD9516 Clock Circuit