Datasheet

AD9629
Rev. 0 | Page 10 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1CLK+
2CLK–
3AVDD
4CSB
5SCLK/DFS
6SDIO/PDWN
7NC
8NC
24 AVDD
23 MODE/OR
22 DCO
21 D11 (MSB)
20 D10
19 D9
18 D8
17 D7
9
(LSB) D
0
10
D1
11
D2
12
D3
13
DRVDD
14
D4
15
D5
16
D6
32
AVDD
31
VIN+
30
VIN–
29
AVDD
28
RBIAS
27
V
CM
26
SENSE
25
VREF
TOP VIEW
(Not to Scale)
AD9629
08540-003
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE MUST BE SOLDERED TO
THE PCB GROUND TO ENSURE PROPER HEAT DISSIPATION
,
NOISE, AND MECHANICAL STRENGTH BENEFITS.
Figure 3. Pin Configuration
Table 8. Pin Function Description
Pin No. Mnemonic Description
0 (EPAD) GND
Exposed Paddle. The exposed paddle is the only ground connection. It must be soldered to the analog
ground of the customer’s PCB to ensure proper functionality and maximize heat dissipation, noise, and
mechanical strength benefits.
1, 2 CLK+, CLK− Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
3, 24, 29, 32 AVDD 1.8 V Supply Pin for ADC Core Domain.
4 CSB SPI Chip Select. Active low enable. 30 kΩ internal pull-up.
5 SCLK/DFS
SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down.
Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down.
DFS high = twos complement output; DFS low = offset binary output.
6 SDIO/PDWN
SPI Data Input/Output (SDIO). Bidirectional SPI data I/O in SPI mode. 30 kΩ internal pull-down.
Non-SPI Mode Power-Down (PDWN). Static control of power-down with 30 kΩ internal pull-down. See
Table 14 for details.
7, 8 NC Do Not Connect.
9 to 12, 14 to 21
D0 (LSB) to
D11 (MSB)
ADC Digital Outputs.
13 DRVDD 1.8 V to 3.3 V Supply Pin for Output Driver Domain.
22 DCO Data Clock Digital Output.
23 MODE/OR
Chip Mode Select Input or Out-of-Range (OR) Digital Output in SPI Mode.
Default = out-of-range (OR) digital output (SPI Register 0x2A[0] = 1).
Option = chip mode select input (SPI Register 0x2A[0] = 0).
Chip power down (SPI Register 0x08[7:5] = 100b).
Chip standby (SPI Register 0x08[7:5] = 101b).
Normal operation, output disabled (SPI Register 0x08[7:5] = 110b).
Normal operation, output enabled (SPI Register 0x08[7:5] = 111b).
Out-of-Range (OR) digital output only in non-SPI mode.
25 VREF 1.0 V Voltage Reference Input/Output. See Table 10.
26 SENSE Reference Mode Selection. See Table 10.
27 VCM Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs.
28 RBIAS Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
30, 31 VIN−, VIN+ ADC Analog Inputs.