Datasheet

AD9633 Data Sheet
Rev. 0 | Page 10 of 40
10073-084
D0–x
D0+x
FCO–
DCO+
CLK+
VIN±x
CLK–
DCO–
FCO+
MSB
N–9
D8
N – 9
D8
N – 8
D7
N – 8
D6
N – 8
D7
N – 9
D6
N – 9
D5
N – 9
D4
N – 9
D3
N – 9
D2
N – 9
D1
N – 9
D0
N – 9
MSB
N – 8
D5
N – 8
t
A
t
DATA
t
EH
t
FCO
t
FRAME
t
PD
t
CPD
t
EL
N – 1
N
Figure 7. Wordwise DDR, One-Lane, 1× Frame, 10-Bit Output Mode
S
YNC
CLK+
t
HSYNC
t
SSYNC
10073-079
Figure 8. SYNC Input Timing Requirements