Datasheet
AD9633 Data Sheet
Rev. 0 | Page 12 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
VIN+A
VIN–A
AVDD
4
PDWN
5
CSB
6
SDIO/OLM
7
SCLK/DTP
24
D0+B
23
D0–B
22
D1+B
21
D1–B
20
FCO+
19
F
CO–
18
DCO+
17
DCO–
16
D0+C
15
D0–C
14
D1+C
13
D1–C
44
SYNC
45
AVDD
46
AVDD
47
VIN–C
48
VI
N+C
43
VCM
42
VREF
41
SENSE
40
RBIA
S
39
AVDD
38
VIN–B
37
VIN+B
25
D0+D
26
D0–D
27
D1+D
28
D1–D
29
DRVDD
30
AVDD
31
CLK+
32
CLK–
33
AVDD
34
AVDD
35
VIN–D
36
VIN+D
8
DRVDD
9
D0+A
10
D0–A
11
D1+A
12
D1–A
AD9633
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE
PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART.
THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR
PROPER OPERATION.
10073-007
Figure 9. 48-Lead LFCSP Pin Configuration, Top View
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
0
AGND,
Exposed Pad
Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides
the analog ground for the part. This exposed pad must be connected to ground for proper
operation.
1
VIN+D ADC D Analog Input True.
2
VIN−D ADC D Analog Input Complement.
3, 4, 7, 34, 39, 45, 46
AVDD 1.8 V Analog Supply Pins.
5, 6
CLK−, CLK+ Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
8, 29
DRVDD Digital Output Driver Supply.
9, 10
D1−D, D1+D Channel D Digital Outputs.
11, 12 D0−D, D0+D Channel D Digital Outputs.
13, 14
D1−C, D1+C Channel C Digital Outputs.
15, 16
D0−C, D0+C Channel C Digital Outputs.
17, 18
DCO−, DCO+ Data Clock Outputs.
19, 20
FCO−, FCO+ Frame Clock Outputs.
21, 22
D1−B, D1+B Channel B Digital Outputs.
23, 24
D0−B, D0+B Channel B Digital Outputs.
25, 26 D1−A, D1+A Channel A Digital Outputs.
27, 28 D0−A, D0+A Channel A Digital Outputs.
30
SCLK/DTP SPI Clock Input/Digital Test Pattern.
31
SDIO/OLM SPI Data Input and Output Bidirectional SPI Data/Output Lane Mode.
32
CSB SPI Chip Select Bar. Active low enable; 30 kΩ internal pull-up.
33
PDWN
Digital Input, 30 kΩ Internal Pull-Down.
PDWN high = power-down device.
PDWN low = run device, normal operation.
35 VIN−A ADC A Analog Input Complement.
36
VIN+A ADC A Analog Input True.
37
VIN+B ADC B Analog Input True.
38 VIN−B ADC B Analog Input Complement.
40
RBIAS Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
41
SENSE Reference Mode Selection.
42
VREF Voltage Reference Input and Output.