Datasheet

Data Sheet AD9633
Rev. 0 | Page 27 of 40
DIGITAL OUTPUTS AND TIMING
The AD9633 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This can be changed to a low power,
reduced signal option (similar to the IEEE 1596.3 standard) via the
SPI. The LVDS driver current is derived on chip and sets the
output current at each output equal to a nominal 3.5 mA. A 100 Ω
differential termination resistor placed at the LVDS receiver
inputs results in a nominal 350 mV swing (or 700 mV p-p
differential) at the receiver.
When operating in reduced range mode, the output current is
reduced to 2 mA. This results in a 200 mV swing (or 400 mV p-
p differential) across a 100 Ω termination at the receiver.
The AD9633 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
placed as close to the receiver as possible. If there is no far-end
receiver termination or there is poor differential trace routing,
timing errors may result. To avoid such timing errors, it is
recommended that the trace length be less than 24 inches and
that the differential output traces be close together and at equal
lengths. An example of the FCO and data stream with proper
trace length and position is shown in Figure 69. Figure 70 shows
the LVDS output timing example in reduced range mode.
10073-074
D0 500mV/DIV
D1 500mV/DIV
DCO 500mV/DIV
FCO 500mV/DIV
4ns/DIV
Figure 69. AD9633-125, LVDS Output Timing Example in ANSI-644 Mode
(Default)
10073-083
D0 400mV/DIV
D1 400mV/DIV
DCO 400mV/DIV
FCO 400mV/DIV
4ns/DIV
Figure 70. AD9633-125, LVDS Output Timing Example in Reduced Range Mode
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histogram
with trace lengths less than 24 inches on standard FR-4 material is
shown in Figure 71.
5.5k
4.5k
5.0k
4.0k
0.5k
1.0k
1.5k
2.0k
2.5k
3.0k
3.5k
0
350ps 400ps 500ps450ps 550ps 600ps 650ps 700ps
TIE JITTER HISTOGRAM (Hits)
500
400
300
200
100
–500
–400
–300
–200
–100
0
–1.0ns –0.5ns 0ns 0.5ns 1.0ns
EYE DIAGRAM VOLTAGE (mV)
EYE: ALL BITS
ULS: 8000/300062
10073-075
Figure 71. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Less than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End
Termination Only