Datasheet

AD9633 Data Sheet
Rev. 0 | Page 28 of 40
400
600
–400
–600
–200
200
0
–1ns –0.5ns 0ns 0.5ns 1ns
EYE DIAGRAM VOLTAGE (mV)
EYE: ALL BITS
ULS: 7000/301593
12k
10k
1k
2k
3k
4k
5k
6k
7k
8k
9k
0
–1ns –0.8ns –0.6ns –0.4ns –0.2ns 0ns 0.2ns 0.4ns 0.8ns0.6ns
TIE JITTER HISTOGRAM (Hits)
10073-076
Figure 72 shows an example of trace lengths exceeding 24 inches
on standard FR-4 material. Notice that the TIE jitter histogram
reflects the decrease of the data eye opening as the edge deviates
from the ideal position. It is the user’s responsibility to determine
if the waveforms meet the timing budget of the design when the
trace lengths exceed 24 inches. Additional SPI options allow the
user to further increase the internal termination (increasing the
current) of all four outputs to drive longer trace lengths. This can
be achieved by programming Register 0x15. Even though this
produces sharper rise and fall times on the data edges and is less
prone to bit errors, the power dissipation of the DRVDD supply
increases when this option is used.
The format of the output data is twos complement by default.
An example of the output coding format can be found in Table 10.
To change the output data format to offset binary, see the
Memory Map section.
Data from each ADC is serialized and provided on a separate
channel in two lanes in DDR mode. The data rate for each serial
stream is equal to 12 bits times the sample clock rate, with a
maximum of 375 Mbps/lane [(12 bits × 125 MSPS)/(2 × 2) =
375 Mbps/lane)]. The lowest typical conversion rate is 10 MSPS.
See the Memory Map section for details on enabling this feature.
Two output clocks are provided to assist in capturing data from
the AD9633. The DCO is used to clock the output data and is
equal to three times the sample clock (CLK) rate for the default
mode of operation. Data is clocked out of the AD9633 and must
be captured on the rising and falling edges of the DCO that
supports double data rate (DDR) capturing. The FCO is used to
signal the start of a new output byte and is equal to the sample
clock rate in 1× frame mode. See the Timing Diagrams section for
more information.
Figure 72. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End
Termination Only
Table 10. Digital Output Coding
Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode
VIN+ − VIN− <−VREF − 0.5 LSB 0000 0000 0000 1000 0000 0000
VIN+ − VIN− −VREF 0000 0000 0000 1000 0000 0000
VIN+ − VIN− 0 V 1000 0000 0000 0000 0000 0000
VIN+ − VIN− +VREF − 1.0 LSB 1111 1111 1111 0111 1111 1111
VIN+ − VIN− >+VREF − 0.5 LSB 1111 1111 1111 0111 1111 1111