Datasheet

AD9633 Data Sheet
Rev. 0 | Page 6 of 40
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4.
Parameter
1, 2
Temp Min Typ Max Unit
CLOCK
3
Input Clock Rate Full 10 1000 MHz
Conversion Rate Full 10 80/105/125 MSPS
Clock Pulse Width High (t
EH
) Full 6.25/4.76/4.00 ns
Clock Pulse Width Low (t
EL
) Full 6.25/4.76/4.00 ns
OUTPUT PARAMETERS
3
Propagation Delay (t
PD
) Full 2.3 ns
Rise Time (t
R
) (20% to 80%) Full 300 ps
Fall Time (t
F
) (20% to 80%) Full 300 ps
FCO Propagation Delay (t
FCO
) Full 1.5 2.3 3.1 ns
DCO Propagation Delay (t
CPD
)
4
Full t
FCO
+ (t
SAMPLE
/12) ns
DCO to Data Delay (t
DATA
)
4
Full (t
SAMPLE
/12) − 300 (t
SAMPLE
/12) (t
SAMPLE
/12) + 300 ps
DCO to FCO Delay (t
FRAME
)
4
Full (t
SAMPLE
/12) − 300 (t
SAMPLE
/12) (t
SAMPLE
/12) + 300 ps
Lane Delay (t
LD
) 90 ps
Data to Data Skew (t
DATA-MAX
− t
DATA-MIN
) Full ±50 ±200 ps
Wake-Up Time (Standby) 25°C 250 ns
Wake-Up Time (Power-Down)
5
25°C 375 μs
Pipeline Latency Full 16 Clock cycles
APERTURE
Aperture Delay (t
A
) 25°C 1 ns
Aperture Uncertainty (Jitter, t
J
) 25°C 135 fs rms
Out-of-Range Recovery Time 25°C 1 Clock cycles
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2
Measured on standard FR-4 material.
3
Can be adjusted via the SPI. The conversion rate is the clock rate after the divider.
4
t
SAMPLE
/12 is based on the number of bits in two LVDS data lanes. t
SAMPLE
= 1/f
S
.
5
Wake-up time is defined as the time required to return to normal operation from power-down mode.