4-Bit, 80/105/125/150 MSPS, 1.
AD9640 TABLE OF CONTENTS Features .............................................................................................. 1 Clock Input Considerations ...................................................... 28 Applications ....................................................................................... 1 Power Dissipation and Standby Mode .................................... 30 Functional Block Diagram .............................................................. 1 Digital Outputs .......
AD9640 REVISION HISTORY 12/09—Rev. A to Rev. B Added CP-64-6 Package .................................................... Universal Changes to Ordering Guide ...........................................................51 6/09—Rev. 0 to Rev. A Changes to Applications Section and Product Highlights Section ............................................................................. 1 Changes to General Description Section ....................................... 3 Changes to Specifications Section.............
AD9640 GENERAL DESCRIPTION The AD9640 is a dual 14-bit, 80/105/125/150 MSPS analog-todigital converter (ADC). The AD9640 is designed to support communications applications where low cost, small size, and versatility are desired. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges.
AD9640 SPECIFICATIONS ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 1.
AD9640 ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 2.
AD9640 ADC AC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 3. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.3 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.
AD9640 ADC AC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ 150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 4. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.3 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.
AD9640 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 5.
AD9640 Parameter DIGITAL OUTPUTS CMOS Mode—DRVDD = 3.3 V High Level Output Voltage (IOH = 50 μA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 μA) CMOS Mode—DRVDD = 1.8 V High Level Output Voltage (IOH = 50 μA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 μA) LVDS Mode—DRVDD = 1.
AD9640 AD9640ABCPZ-80 Parameter CMOS Mode Pipeline Delay (Latency) LVDS Mode Pipeline Delay (Latency) Channel A/Channel B Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Wake-Up Time 3 OUT-OF-RANGE RECOVERY TIME 1 2 3 Temp Full AD9640ABCPZ-105/ AD9640BCPZ-80 Typ Max 12 12/12.5 Min Full Full Full Full Min 1.0 0.1 350 2 AD9640BCPZ-105 Typ Max 12 12/12.5 1.0 0.1 350 2 Unit Cycles Cycles ns ps rms μs Cycles Conversion rate is the clock rate after the divider.
AD9640 TIMING SPECIFICATIONS Table 8. Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO SPORT TIMING REQUIREMENTS tCSSCLK tSSCLKSDO tSSCLKSDFS Conditions Min Typ SYNC to rising edge of CLK setup time SYNC to rising edge of CLK hold time Max 0.24 0.
AD9640 N+2 N+1 N+3 N N+4 N+8 tA N+5 N+6 N+7 tCLK CLK+ CLK– tPD CH A/CH B DATA A CH A/CH B FAST DETECT A B N – 13 B N–7 A B N – 12 A B N–6 A B N – 11 A B N–5 A B N – 10 A B N–4 A B N–9 A B N–3 A B N–8 A B N–2 tDCO A B N–7 A B N–1 A B A N–6 A B B N–5 A N B N+1 A N–4 A N+2 tCLK 06547-089 DCO+ DCO– Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode 1 Through Fast Detect Mode 5) CLK+ tHSYNC 06547-072 tSSYNC SYNC Figure 4.
AD9640 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 9.
AD9640 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DRGND D5B D4B D3B D2B D1B D0B (LSB) DVDD FD3B FD2B FD1B FD0B SYNC CSB CLK– CLK+ PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD9640 PARALLEL CMOS TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCLK/DFS SDIO/DCS AVDD AVDD VIN+B VIN–B RBIAS CML SENSE VREF VIN–A VIN+A AVDD SMI SDFS SMI SCLK/PDWN SMI SDO/OEB NOTES 1.
AD9640 Pin No.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DRGND D0+ (LSB) D0– (LSB) FD3+ FD3– FD2+ FD2– DVDD FD1+ FD1– FD0+ FD0– SYNC CSB CLK– CLK+ AD9640 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD9640 PARALLEL LVDS TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCLK/DFS SDIO/DCS AVDD AVDD VIN+B VIN–B RBIAS CML SENSE VREF VIN–A VIN+A AVDD SMI SDFS SMI SCLK/PDWN SMI SDO/OEB NOTES 1. NC = NO CONNECT. 2.
AD9640 Pin No. Mnemonic Digital Inputs 52 SYNC Digital Outputs 63 D0+ (LSB) 62 D0− (LSB) 3 D1+ 2 D1− 5 D2+ 4 D2− 7 D3+ 6 D3− 9 D4+ 8 D4− 13 D5+ 12 D5− 15 D6+ 14 D6− 17 D7+ 16 D7− 19 D8+ 18 D8− 23 D9+ 22 D9− 26 D10+ 25 D10− 28 D11+ 27 D11− 30 D12+ 29 D12− 32 D13+ (MSB) 31 D13− (MSB) 11 DCO+ 10 DCO− SPI Control 48 SCLK/DFS 47 SDIO/DCS 51 CSB Signal Monitor Ports 33 SMI SDO/OEB 35 SMI SDFS 34 SMI SCLK/PDWN Type Function Input Digital Synchronization Pin. Slave mode only.
AD9640 EQUIVALENT CIRCUITS DVDD 1kΩ SCLK/DFS VIN 06547-011 06547-004 26kΩ Figure 8. Equivalent Analog Input Circuit Figure 12. Equivalent SCLK/DFS Input Circuit AVDD 1kΩ 1.2V 10kΩ SENSE 10kΩ CLK+ 06547-005 06547-009 CLK– Figure 13. Equivalent SENSE Circuit Figure 9. Equivalent Clock Input Circuit DRVDD DVDD 26kΩ DVDD 1kΩ 06547-081 06547-010 CSB DRGND Figure 10. Digital Output Figure 14.
AD9640 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V; DVDD = 1.8 V; DRVDD = 3.3 V; sample rate = 150 MSPS, DCS enabled, 1 V internal reference; 2 V p-p differential input; VIN = −1.0 dBFS; and 64k sample; TA = 25°C, unless otherwise noted. 0 0 150MSPS 2.3MHz @ –1dBFS SNR = 71.9dBc (72.9dBFS) ENOB = 11.
AD9640 0 0 150MSPS 440MHz @ –1dBFS SNR = 65dBc (66dBFS) ENOB = 10.4 BITS SFDR = 70.0dB –20 AMPLITUDE (dBFS) –40 SECOND HARMONIC –60 THIRD HARMONIC –80 –60 THIRD HARMONIC SECOND HARMONIC –80 –100 06547-086 –100 –40 –120 0 10 20 30 40 50 60 06547-093 AMPLITUDE (dBFS) –20 125MSPS 70MHz @ –1dBFS SNR = 71.8dBc (72.8dBFS) ENOB = 11.7 BITS SFDR = 85dBc –120 0 70 10 20 FREQUENCY (MHz) Figure 22. AD9640-150 Single-Tone FFT with fIN = 440 MHz 40 50 60 Figure 25.
AD9640 120 95 SFDR = +25°C 85 SNR (dBFS) 60 SFDR (dBc) 40 SNR (dBc) 20 –70 –60 –50 –40 –30 –20 75 SFDR = +85°C SNR = –40°C 65 06547-061 –80 SFDR = –40°C 70 85dB REFERENCE LINE 0 –90 80 SNR = +25°C SNR = +85°C 60 0 0 –10 50 100 INPUT AMPLITUDE (dBFS) 06547-088 80 SNR/SFDR (dBc) SNR/SFDR (dBc AND dBFS) 90 SFDR (dBFS) 100 150 200 250 300 350 400 450 INPUT FREQUENCY (MHz) Figure 31. AD9640-150 Single-Tone SNR/SFDR vs.
AD9640 0 0 –20 SFDR (dBc) AMPLITUDE (dBFS) –40 –60 IMD3 (dBc) IMD3 (dBFS) –80 –40 –60 –80 SFDR (dBFS) –100 –120 –90 06547-064 –100 –78 –66 –54 –42 –30 –120 –6 –18 06547-066 SNR/SFDR (dBc AND dBFS) –20 150 MSPS 169.1MHz @–7dBFS 172.1MHz @–7dBFS SFDR = 83.8dBc (90.8dBFS) 0 10 20 INPUT AMPLITUDE (dBFS) Figure 34. AD9640-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 150 MSPS 50 60 70 0 NPR = 64.7dBc NOTCH @ 18.
AD9640 10 100 1.3 LSB rms 95 SFDR DCS ON 90 SNR/SFDR (dBc) NUMBER OF HITS (1M) 8 6 4 85 SFDR DCS OFF 80 SNR DCS ON 75 70 2 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 OUTPUT CODE N+4 60 20 06547-079 0 Figure 43. AD9640 SNR/SFDR vs. Duty Cycle with fIN = 10.3 MHz 2.0 90 SFDR 1.5 1.0 85 SNR/SFDR (dBc) 0.5 0 –0.5 –1.0 80 75 SNR 06547-068 –1.5 –2.0 0 2048 4096 6144 8192 70 0.5 10,240 12,288 14,336 16,384 OUTPUT CODE 0.4 0.3 0.2 0.1 0 –0.1 –0.2 06547-069 –0.
AD9640 THEORY OF OPERATION The AD9640 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any fS/2 frequency segment from dc to 200 MHz using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance.
AD9640 The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD9640 (see Figure 46), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. An alternative to using a transformer coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver. An example is shown in Figure 50. See the AD8352 data sheet for more information.
AD9640 VOLTAGE REFERENCE VIN+A/VIN+B VIN–A/VIN–B A stable and accurate voltage reference is built into the AD9640. The input range can be adjusted by varying the reference voltage applied to the AD9640, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are summarized in the next few sections.
AD9640 This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9640, while preserving the fast rise and fall times of the signal that are critical to a low jitter performance. 2.0 1.5 1.0 0 MINI-CIRCUITS ADT1–1WT, 1:1Z 0.1µF XFMR 0.1µF –0.5 CLOCK INPUT –1.0 CLK+ ADC AD9640 100Ω 50Ω 0.1µF CLK– –1.5 –2.5 –40 –20 0 20 40 60 06547-035 –2.0 SCHOTTKY DIODES: HSMS2822 0.1µF 06547-099 REFERENCE VOLTAGE ERROR (mV) 2.5 Figure 56.
AD9640 CLK+ can be directly driven from a CMOS gate. Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages up to 3.6 V, making the selection of the drive logic voltage very flexible. VCC 0.1µF 1kΩ CLOCK INPUT OPTIONAL 0.1µF 100Ω AD951x CMOS DRIVER CLK+ ADC AD9640 1kΩ 50Ω1 CLK– 150Ω 39kΩ 06547-038 0.1µF RESISTOR IS OPTIONAL Figure 60. Single-Ended 1.
AD9640 IAVDD 0.5 0.3 TOTAL POWER 0.5 0.2 IDRVDD 0.25 0 25 50 75 100 125 0 150 0.5 TOTAL POWER 0.5 0.2 IDRVDD 0.25 0.1 IDVDD 0 0 25 50 75 100 SUPPLY CURRENT (A) 0.3 0.75 0 125 ENCODE FREQUENCY (MHz) Figure 64. AD9640-125 Power and Current vs. Clock Frequency 06547-075 TOTAL POWER (W) 0.4 IAVDD 25 0 50 75 100 ENCODE FREQUENCY (MHz) Figure 65. AD9640-105 Power and Current vs. Clock Frequency 0.75 0.3 IAVDD 0.5 0.2 TOTAL POWER 0.1 0.
AD9640 DIGITAL OUTPUTS Digital Output Enable Function (OEB) The AD9640 output drivers can be configured to interface with 1.8 V to 3.3 V CMOS logic families by matching DRVDD to the digital supply of the interfaced logic. The AD9640 can also be configured for LVDS outputs using a DRVDD supply voltage of 1.8 V. The AD9640 has a flexible three-state ability for the digital output pins. The three-state mode is enabled using the SMI SDO/OEB pin or through the SPI interface.
AD9640 ADC OVERRANGE AND GAIN CONTROL In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overflow indicator provides after-the-fact information on the state of the analog input that is of limited usefulness. Therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs.
AD9640 When the fast detect mode select bits are set to 0b001, 0b010, or 0b011, a subset of the fast detect output pins is available. In these modes, the fast detect output pins have a latency of six clock cycles. Table 19 shows the corresponding ADC input levels when the fast detect mode select bits are set to 0b001 (that is, when ADC fast magnitude is presented on the FD[3:1] pins). Table 19.
AD9640 similarly, corresponds to the fine lower threshold bits, except that it is asserted only if the input magnitude is less than the value programmed in the fine lower threshold register after the dwell time elapses. The dwell time is set by the 16-bit dwell time value located at Address 0x10A and Address 0x10B and is set in units of ADC input clock cycles ranging from 1 to 65,535. The fine lower threshold register is a 13-bit register that is compared with the magnitude at the output of the ADC.
AD9640 SIGNAL MONITOR The signal monitor result values can be obtained from the part by reading back internal registers at Address 0x116 to Address 0x11B, using the SPI port or the signal monitor SPORT output. The output contents of the SPI-accessible signal monitor registers are set via the two signal monitor mode bits of the signal monitor control register. Both ADC channels must be configured for the same signal monitor mode (Address 0x112).
AD9640 Figure 69 illustrates the rms magnitude monitoring logic. DOWN COUNTER IS COUNT = 1? LOAD CLEAR ACCUMULATOR TO MEMORY SIGNAL MONITOR MAP/SPORT HOLDING REGISTER (SMR) LOAD 06547-092 FROM INPUT PORTS Figure 69. ADC Input RMS Magnitude Monitoring Block Diagram For rms magnitude mode, the value in the signal monitor result (SMR) register is a 20-bit fixed-point number. The following equation can be used to determine the rms magnitude in dBFS from the MAG value in the register.
AD9640 DC Correction Bandwidth SIGNAL MONITOR SPORT OUTPUT The dc correction circuit is a high-pass filter with a programmable bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS). The bandwidth is controlled by writing Bits[5:2] of the signal monitor dc correction control register, located at Address 0x10C.
AD9640 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9640 includes built-in test features to enable verification of the integrity of each channel as well as to facilitate board level debugging. A built-in self-test (BIST) feature is included that verifies the integrity of the digital data path of the AD9640. Various output test options are also provided to place predictable values on the outputs of the AD9640.
AD9640 CHANNEL/CHIP SYNCHRONIZATION The AD9640 has a SYNC input that allows the user flexible synchronization options for synchronizing the internal blocks. The clock divider sync feature is useful to guarantee synchronized sample clocks across multiple ADCs. The signal monitor block can also be synchronized using the SYNC input allowing properties of the input signal to be measured during a specific time period.
AD9640 SERIAL PORT INTERFACE (SPI) The AD9640 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This gives the user added flexibility and customization depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, which are documented in the Memory Map section.
AD9640 CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES In applications that do not interface to the SPI control registers, the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin, and the SMI SCLK/PDWN pin serve as standalone, CMOScompatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer, output data format, output enable, and power-down feature control.
AD9640 MEMORY MAP READING THE MEMORY MAP TABLE Logic Levels Each row in the memory map table has eight bit locations. The memory map is roughly divided into four sections: chip configuration and ID register map (Address 0x00 to Address 0x02); ADC setup, control, and test (Address 0x08 to Address 0x25); the channel index and transfer register map (Address 0x05 to Address 0xFF); and digital feature control (Address 0x100 to Address 0x11B).
AD9640 EXTERNAL MEMORY MAP Table 25.
AD9640 Addr (Hex) 0x0E 0x10 0x14 Register Name BIST Enable (Local) Offset Adjust (Local) Output Mode Bit 7 (MSB) Open Bit 6 Open Open Open Drive strength 0 V to 3.3 V CMOS or ANSI LVDS: 1 V to 1.8 V CMOS or reduced: LVDS (global) Invert DCO clock Output type 0 = CMOS 1 = LVDS (global) Open Output enable bar (local) Open Open Open Open Open 0x16 Clock Phase Control (Global) 0x17 DCO Output Delay (Global) Open 0x18 VREF Select (Global) Reference voltage selection 00 = 1.25 V p-p 01 = 1.
AD9640 Addr (Hex) 0x10C Register Name Signal Monitor DC Correction Control (Global) 0x10D Signal Monitor DC Value Channel A Register 0 (Global) Signal Monitor DC Value Channel A Register 1 (Global) Signal Monitor DC Value Channel B Register 0 (Global) Signal Monitor DC Value Channel B Register 1 (Global) Signal Monitor SPORT Control (Global) 0x10E 0x10F 0x110 0x111 0x112 Signal Monitor Control (Global) 0x113 Signal Monitor Period Register 0 (Global) Signal Monitor Period Register 1 (Global) Signa
AD9640 Addr (Hex) 0x11A 0x11B Register Name Signal Monitor Result Channel B Register 1 (Global) Signal Monitor Result Channel B Register 2 (Global) Bit 7 (MSB) Bit 6 Bit 5 Open Open Open Bit 4 Bit 3 Bit 2 Signal Monitor Result Channel B[15:8] Open MEMORY MAP REGISTER DESCRIPTION For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
AD9640 Bit 5—Peak Power Output Enable Table 26. DC Correction Bandwidth DC Correction Control Register 0x10C[5:2] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bandwidth (Hz) 1218.56 609.28 304.64 152.32 76.16 38.08 19.04 9.52 4.76 2.38 1.19 0.60 0.30 0.15 0.15 0.15 Bit 1—DC Correction for Signal Path Enable Setting Bit 1 high causes the output of the dc measurement block to be summed with the data in the signal path to remove the dc offset from the signal path.
AD9640 Signal Monitor Result Channel A (Register 0x116 to Register 0x118) Register 0x116, Bits[7:0]—Signal Monitor Result Channel A[7:0] Signal Monitor Result Channel B (Register 0x119 to Register 0x11B) Register 0x119, Bits[7:0]— Signal Monitor Result Channel B[7:0] Register 0x117, Bits[7:0]—Signal Monitor Result Channel A[15:8] Register 0x11A, Bits[7:0]—Signal Monitor Result Channel B[15:8] Register 0x118, Bits[7:4]—Reserved Register 0x11B, Bits[7:4]—Reserved Register 0x118, Bits[3:0]—Signal Monitor
AD9640 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9640 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and Ground Recommendations When connecting power to the AD9640, it is recommended that two separate 1.
AD9640 OUTLINE DIMENSIONS 0.60 MAX 9.00 BSC SQ 0.60 MAX 64 1 49 48 PIN 1 INDICATOR PIN 1 INDICATOR 8.75 BSC SQ 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 16 17 33 32 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 12° MAX FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 7.25 7.10 SQ 6.95 EXPOSED PAD (BOTTOM VIEW) 0.
AD9640 ORDERING GUIDE Model AD9640ABCPZ-150 1, 2 AD9640ABCPZ-1251, 2 AD9640ABCPZ-1051, 2 AD9640ABCPZ-801, 2 AD9640ABCPZRL7-801, 2 AD9640BCPZ-1501 AD9640BCPZ-1251 AD9640BCPZ-1051 AD9640BCPZ-801 AD9640-150EBZ1 AD9640-125EBZ1 AD9640-105EBZ1 AD9640-80EBZ1 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Pa
AD9640 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06547-0-12/09(B) Rev.
