Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- PRODUCT HIGHLIGHTS
- TABLE OF CONTENTS
- REVISION HISTORY
- GENERAL DESCRIPTION
- SPECIFICATIONS
- ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105
- ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ150
- ADC AC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105
- ADC AC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ 150
- DIGITAL SPECIFICATIONS
- SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ105
- SWITCHING SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ150
- TIMING SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
- EQUIVALENT CIRCUITS
- TYPICAL PERFORMANCE CHARACTERISTICS
- THEORY OF OPERATION
- ADC OVERRANGE AND GAIN CONTROL
- SIGNAL MONITOR
- BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
- CHANNEL/CHIP SYNCHRONIZATION
- SERIAL PORT INTERFACE (SPI)
- MEMORY MAP
- READING THE MEMORY MAP TABLE
- EXTERNAL MEMORY MAP
- MEMORY MAP REGISTER DESCRIPTION
- Sync Control (Register 0x100)
- Fast Detect Control (Register 0x104)
- Fine Upper Threshold (Register 0x106 and Register 0x107)
- Fine Lower Threshold (Register 0x108 and Register 0x109)
- Signal Monitor DC Correction Control (Register 0x10C)
- Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E)
- Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110)
- Signal Monitor SPORT Control (Register 0x111)
- Signal Monitor Control (Register 0x112)
- Signal Monitor Period (Register 0x113 to Register 0x115)
- Signal Monitor Result Channel A (Register 0x116 to Register 0x118)
- Signal Monitor Result Channel B (Register 0x119 to Register 0x11B)
- APPLICATIONS INFORMATION
- OUTLINE DIMENSIONS

AD9640
Rev. B | Page 10 of 52
Parameter Temperature Min Typ Max Unit
DIGITAL OUTPUTS
CMOS Mode—DRVDD = 3.3 V
High Level Output Voltage (I
OH
= 50 μA) Full 3.29 V
High Level Output Voltage (I
OH
= 0.5 mA) Full 3.25 V
Low Level Output Voltage (I
OL
= 1.6 mA) Full 0.2 V
Low Level Output Voltage (I
OL
= 50 μA) Full 0.05 V
CMOS Mode—DRVDD = 1.8 V
High Level Output Voltage (I
OH
= 50 μA) Full 1.79 V
High Level Output Voltage (I
OH
= 0.5 mA) Full 1.75 V
Low Level Output Voltage (I
OL
= 1.6 mA) Full 0.2 V
Low Level Output Voltage (I
OL
= 50 μA) Full 0.05 V
LVDS Mode—DRVDD = 1.8 V
Differential Output Voltage (V
OD
), ANSI Mode Full 250 350 450 mV
Output Offset Voltage (V
OS
), ANSI Mode Full 1.15 1.25 1.35 V
Differential Output Voltage (V
OD
), Reduced Swing Mode Full 150 200 280 mV
Output Offset Voltage (V
OS
), Reduced Swing Mode Full 1.15 1.25 1.35 V
1
Pull up.
2
Pull down.
SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND
AD9640BCPZ-105
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, unless otherwise noted.
Table 6.
Parameter Temp
AD9640ABCPZ-80
AD9640BCPZ-80
AD9640ABCPZ-105/
AD9640BCPZ-105
Unit
Min Typ Max Min Typ Max
CLOCK INPUT PARAMETERS
Input Clock Rate Full 625 625 MHz
Conversion Rate
DCS Enabled
1
Full 20 80 20 105 MSPS
DCS Disabled
1
Full 10 80 10 105 MSPS
CLK Period—Divide by 1 Mode (t
CLK
) Full 12.5 9.5 ns
CLK Pulse Width High
Divide by 1 Mode, DCS Enabled Full 3.75 6.25 8.75 2.85 4.75 6.65 ns
Divide by 1 Mode, DCS Disabled Full 5.63 6.25 6.88 4.28 4.75 5.23 ns
Divide by 2 Mode, DCS Enabled Full 1.6 1.6 ns
Divide by 3 Through 8, DCS Enabled Full 0.8 0.8 ns
DATA OUTPUT PARAMETERS (DATA, FD)
CMOS Mode—DRVDD = 3.3 V
Data Propagation Delay (t
PD
)
2
Full 2.2 4.5 6.4 2.2 4.5 6.4 ns
DCO Propagation Delay (t
DCO
) Full 3.8 5.0 6.8 3.8 5.0 6.8 ns
Setup Time (t
S
) Full 6.25 5.25 ns
Hold Time (t
H
) Full 5.75 4.25 ns
CMOS Mode—DRVDD = 1.8 V
Data Propagation Delay (t
PD
)
2
Full 2.4 5.2 6.9 2.4 5.2 6.9 ns
DCO Propagation Delay (t
DCO
) Full 4.0 5.6 7.3 4.0 5.6 7.3 ns
LVDS Mode—DRVDD = 1.8 V
Data Propagation Delay (t
PD
)
2
Full 3.0 3.7 4.4 3.0 3.7 4.4 ns
DCO Propagation Delay (t
DCO
) Full 5.4 7.0 8.4 5.2 6.4 7.6 ns