Datasheet

AD9640
Rev. B | Page 12 of 52
TIMING SPECIFICATIONS
Table 8.
Parameter Conditions Min Typ Max Unit
SYNC TIMING REQUIREMENTS
t
SSYNC
SYNC to rising edge of CLK setup time 0.24 ns
t
HSYNC
SYNC to rising edge of CLK hold time 0.40 ns
SPI TIMING REQUIREMENTS
t
DS
Setup time between the data and the rising edge of SCLK 2 ns
t
DH
Hold time between the data and the rising edge of SCLK 2 ns
t
CLK
Period of the SCLK 40 ns
t
S
Setup time between CSB and SCLK 2 ns
t
H
Hold time between CSB and SCLK 2 ns
t
HIGH
SCLK pulse width high 10 ns
t
LOW
SCLK pulse width low 10 ns
t
EN_SDIO
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
10 ns
t
DIS_SDIO
Time required for the SDIO pin to switch from an output to
an input relative to the SCLK rising edge
10 ns
SPORT TIMING REQUIREMENTS
t
CSSCLK
Delay from rising edge of CLK+ to rising edge of SMI SCLK 3.2 4.5 6.2 ns
t
SSCLKSDO
Delay from rising edge of SMI SCLK to SMI SDO −0.4 0 +0.4 ns
t
SSCLKSDFS
Delay from rising edge of SMI SCLK to SMI SDFS −0.4 0 +0.4 ns
Timing Diagrams
CLK+
DCOA/DCOB
C
H A/B DAT
A
N
N+ 1
N+2
N+ 3
N+ 4
N+ 5
N+ 6
N+ 7
N+ 8
N – 12 N – 11 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4
N – 13
CLK–
t
CLK
t
PD
t
S
t
H
t
DCO
t
CLK
t
A
CH A/B FAST
DETECT
N – 1 N + 2 N + 3 N + 4 N + 5 N + 6N – 3 N – 2
06547-021
N – 10
N + 1
N
Figure 2. CMOS Output Mode Data and Fast Detect Output Timing (Fast Detect Mode 0)