Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- PRODUCT HIGHLIGHTS
- TABLE OF CONTENTS
- REVISION HISTORY
- GENERAL DESCRIPTION
- SPECIFICATIONS
- ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105
- ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ150
- ADC AC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105
- ADC AC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ 150
- DIGITAL SPECIFICATIONS
- SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ105
- SWITCHING SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ150
- TIMING SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
- EQUIVALENT CIRCUITS
- TYPICAL PERFORMANCE CHARACTERISTICS
- THEORY OF OPERATION
- ADC OVERRANGE AND GAIN CONTROL
- SIGNAL MONITOR
- BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
- CHANNEL/CHIP SYNCHRONIZATION
- SERIAL PORT INTERFACE (SPI)
- MEMORY MAP
- READING THE MEMORY MAP TABLE
- EXTERNAL MEMORY MAP
- MEMORY MAP REGISTER DESCRIPTION
- Sync Control (Register 0x100)
- Fast Detect Control (Register 0x104)
- Fine Upper Threshold (Register 0x106 and Register 0x107)
- Fine Lower Threshold (Register 0x108 and Register 0x109)
- Signal Monitor DC Correction Control (Register 0x10C)
- Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E)
- Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110)
- Signal Monitor SPORT Control (Register 0x111)
- Signal Monitor Control (Register 0x112)
- Signal Monitor Period (Register 0x113 to Register 0x115)
- Signal Monitor Result Channel A (Register 0x116 to Register 0x118)
- Signal Monitor Result Channel B (Register 0x119 to Register 0x11B)
- APPLICATIONS INFORMATION
- OUTLINE DIMENSIONS
AD9640
Rev. B | Page 18 of 52
Pin No. Mnemonic Type Function
Digital Inputs
52 SYNC Input Digital Synchronization Pin. Slave mode only.
Digital Outputs
63 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True.
62 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement.
3 D1+ Output Channel A/Channel B LVDS Output Data 1—True.
2 D1− Output Channel A/Channel B LVDS Output Data 1—Complement.
5 D2+ Output Channel A/Channel B LVDS Output Data 2—True.
4 D2− Output Channel A/Channel B LVDS Output Data 2—Complement.
7 D3+ Output Channel A/Channel B LVDS Output Data 3—True.
6 D3− Output Channel A/Channel B LVDS Output Data 3—Complement.
9 D4+ Output Channel A/Channel B LVDS Output Data 4—True.
8 D4− Output Channel A/Channel B LVDS Output Data 4—Complement.
13 D5+ Output Channel A/Channel B LVDS Output Data 5—True.
12 D5− Output Channel A/Channel B LVDS Output Data 5—Complement.
15 D6+ Output Channel A/Channel B LVDS Output Data 6 —True.
14 D6− Output Channel A/Channel B LVDS Output Data 6—Complement.
17 D7+ Output Channel A/Channel B LVDS Output Data 7—True.
16 D7− Output Channel A/Channel B LVDS Output Data 7—Complement.
19 D8+ Output Channel A/Channel B LVDS Output Data 8—True.
18 D8− Output Channel A/Channel B LVDS Output Data 8—Complement.
23 D9+ Output Channel A/Channel B LVDS Output Data 9—True.
22 D9− Output Channel A/Channel B LVDS Output Data 9—Complement.
26 D10+ Output Channel A/Channel B LVDS Output Data 10—True.
25 D10− Output Channel A/Channel B LVDS Output Data 10—Complement.
28 D11+ Output Channel A/Channel B LVDS Output Data 11—True.
27 D11− Output Channel A/Channel B LVDS Output Data 11—Complement.
30 D12+ Output Channel A/Channel B LVDS Output Data 12—True.
29 D12− Output Channel A/Channel B LVDS Output Data 12—Complement.
32 D13+ (MSB) Output Channel A/Channel B LVDS Output Data 13—True.
31 D13− (MSB) Output Channel A/Channel B LVDS Output Data 13—Complement.
11 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True.
10 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement.
SPI Control
48 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode.
47 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer in External Pin Mode.
51 CSB Input SPI Chip Select (Active Low).
Signal Monitor Ports
33 SMI SDO/OEB Input/Output Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode.
35 SMI SDFS Output Signal Monitor Serial Data Frame Sync.
34 SMI SCLK/PDWN Input/Output Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.