Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- PRODUCT HIGHLIGHTS
- TABLE OF CONTENTS
- REVISION HISTORY
- GENERAL DESCRIPTION
- SPECIFICATIONS
- ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105
- ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ150
- ADC AC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105
- ADC AC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ 150
- DIGITAL SPECIFICATIONS
- SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ105
- SWITCHING SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ150
- TIMING SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
- EQUIVALENT CIRCUITS
- TYPICAL PERFORMANCE CHARACTERISTICS
- THEORY OF OPERATION
- ADC OVERRANGE AND GAIN CONTROL
- SIGNAL MONITOR
- BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
- CHANNEL/CHIP SYNCHRONIZATION
- SERIAL PORT INTERFACE (SPI)
- MEMORY MAP
- READING THE MEMORY MAP TABLE
- EXTERNAL MEMORY MAP
- MEMORY MAP REGISTER DESCRIPTION
- Sync Control (Register 0x100)
- Fast Detect Control (Register 0x104)
- Fine Upper Threshold (Register 0x106 and Register 0x107)
- Fine Lower Threshold (Register 0x108 and Register 0x109)
- Signal Monitor DC Correction Control (Register 0x10C)
- Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E)
- Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110)
- Signal Monitor SPORT Control (Register 0x111)
- Signal Monitor Control (Register 0x112)
- Signal Monitor Period (Register 0x113 to Register 0x115)
- Signal Monitor Result Channel A (Register 0x116 to Register 0x118)
- Signal Monitor Result Channel B (Register 0x119 to Register 0x11B)
- APPLICATIONS INFORMATION
- OUTLINE DIMENSIONS

AD9640
Rev. B | Page 2 of 52
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Specifications ..................................................................................... 5
ADC DC Specifications—AD9640ABCPZ-80,
AD9640BCPZ-80, AD9640ABCPZ-105, and
AD9640BCPZ-105 ......................................................................... 5
ADC DC Specifications—AD9640ABCPZ-125,
AD9640BCPZ-125, AD9640ABCPZ-150, and
AD9640BCPZ-150 ......................................................................... 6
ADC AC Specifications—AD9640ABCPZ-80,
AD9640BCPZ-80, AD9640ABCPZ-105, and
AD9640BCPZ-105 ......................................................................... 7
ADC AC Specifications—AD9640ABCPZ-125,
AD9640BCPZ-125, AD9640ABCPZ-150, and
AD9640BCPZ 150 ......................................................................... 8
Digital Specifications ................................................................... 9
Switching Specifications—AD9640ABCPZ-80,
AD9640BCPZ-80, AD9640ABCPZ-105, and
AD9640BCPZ-105 ..................................................................... 10
Switching Specifications—AD9640ABCPZ-125,
AD9640BCPZ-125, AD9640ABCPZ-150, and
AD9640BCPZ-150 ..................................................................... 11
Timing Specifications ................................................................ 12
Absolute Maximum Ratings .......................................................... 14
Thermal Characteristics ............................................................ 14
ESD Caution ................................................................................ 14
Pin Configurations and Function Descriptions ......................... 15
Equivalent Circuits ......................................................................... 19
Typical Performance Characteristics ........................................... 20
Theory of Operation ...................................................................... 25
ADC Architecture ...................................................................... 25
Analog Input Considerations .................................................... 25
Voltage Reference ....................................................................... 27
Clock Input Considerations ...................................................... 28
Power Dissipation and Standby Mode .................................... 30
Digital Outputs ........................................................................... 31
Timing ......................................................................................... 31
ADC Overrange and Gain Control .............................................. 32
Fast Detect Overview ................................................................. 32
ADC Fast Magnitude ................................................................. 32
ADC Overrange (OR) ................................................................ 33
Gain Switching ............................................................................ 33
Signal Monitor ................................................................................ 35
Peak Detector Mode................................................................... 35
RMS/MS Magnitude Mode ......................................................... 35
Threshold Crossing Mode ......................................................... 36
Additional Control Bits ............................................................. 36
DC Correction ............................................................................ 36
Signal Monitor SPORT Output ................................................ 37
Built-In Self-Test (BIST) and Output Test .................................. 38
Built-In Self-Test (BIST) ............................................................ 38
Output Test Modes ..................................................................... 38
Channel/Chip Synchronization .................................................... 39
Serial Port Interface (SPI) .............................................................. 40
Configuration Using the SPI ..................................................... 40
Hardware Interface ..................................................................... 40
Configuration Without the SPI ................................................ 41
SPI Accessible Features .............................................................. 41
Memory Map .................................................................................. 42
Reading the Memory Map Table .............................................. 42
External Memory Map .............................................................. 43
Memory Map Register Description ......................................... 46
Applications Information .............................................................. 49
Design Guidelines ...................................................................... 49
Outline Dimensions ....................................................................... 50
Ordering Guide .......................................................................... 51