Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- PRODUCT HIGHLIGHTS
- TABLE OF CONTENTS
- REVISION HISTORY
- GENERAL DESCRIPTION
- SPECIFICATIONS
- ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105
- ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ150
- ADC AC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105
- ADC AC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ 150
- DIGITAL SPECIFICATIONS
- SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ105
- SWITCHING SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ150
- TIMING SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
- EQUIVALENT CIRCUITS
- TYPICAL PERFORMANCE CHARACTERISTICS
- THEORY OF OPERATION
- ADC OVERRANGE AND GAIN CONTROL
- SIGNAL MONITOR
- BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
- CHANNEL/CHIP SYNCHRONIZATION
- SERIAL PORT INTERFACE (SPI)
- MEMORY MAP
- READING THE MEMORY MAP TABLE
- EXTERNAL MEMORY MAP
- MEMORY MAP REGISTER DESCRIPTION
- Sync Control (Register 0x100)
- Fast Detect Control (Register 0x104)
- Fine Upper Threshold (Register 0x106 and Register 0x107)
- Fine Lower Threshold (Register 0x108 and Register 0x109)
- Signal Monitor DC Correction Control (Register 0x10C)
- Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E)
- Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110)
- Signal Monitor SPORT Control (Register 0x111)
- Signal Monitor Control (Register 0x112)
- Signal Monitor Period (Register 0x113 to Register 0x115)
- Signal Monitor Result Channel A (Register 0x116 to Register 0x118)
- Signal Monitor Result Channel B (Register 0x119 to Register 0x11B)
- APPLICATIONS INFORMATION
- OUTLINE DIMENSIONS
AD9640
Rev. B | Page 20 of 52
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V; DVDD = 1.8 V; DRVDD = 3.3 V; sample rate = 150 MSPS, DCS enabled, 1 V internal reference;
2 V p-p differential input; VIN = −1.0 dBFS; and 64k sample; T
A
= 25°C, unless otherwise noted.
0
–120
0
06547-050
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
10 20 30 40 50 7060
150MSPS
2.3MHz @ –1dBFS
SNR = 71.9dBc (72.9dBFS)
ENOB = 11.8 BITS
SFDR = 86dBc
SECOND HARMONIC
THIRD HARMONIC
Figure 16. AD9640-150 Single-Tone FFT with f
IN
= 2.3 MHz
0
–120
0
06547-051
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
10 20 30 40 50 7060
150MSPS
30.3MHz @ –1dBFS
SNR = 71.7dBc (72.7dBFS)
ENOB = 11.8 BITS
SFDR = 89.9dBc
SECOND HARMONIC
THIRD HARMONIC
Figure 17. AD9640-150 Single-Tone FFT with f
IN
= 30.3 MHz
0
–120
0
06547-052
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
10 20 30 40 50 7060
150MSPS
70MHz @ –1dBFS
SNR = 71.5dBc (72.5dBFS)
ENOB = 11.7 BITS
SFDR = 84dBc
SECOND HARMONIC
THIRD HARMONIC
Figure 18. AD9640-150 Single-Tone FFT with f
IN
= 70 MHz
0
–120
0
06547-053
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
10 20 30 40 50 7060
150MSPS
140.3MHz @ –1dBFS
SNR = 70.9dBc (71.9dBFS)
ENOB = 11.6 BITS
SFDR = 85.1dBc
SECOND HARMONIC
THIRD HARMONIC
Figure 19. AD9640-150 Single-Tone FFT with f
IN
= 140.3 MHz
0
–120
0
06547-054
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
10 20 30 40 50 7060
150MSPS
200.3MHz @ –1dBFS
SNR = 70dBc (71dBFS)
ENOB = 11.5 BITS
SFDR = 80dBc
SECOND HARMONIC
THIRD HARMONIC
Figure 20. AD9640-150 Single-Tone FFT with f
IN
= 200.3 MHz
0
–120
0
06547-085
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
10 20 30 40 50 7060
150MSPS
337MHz @ –1dBFS
SNR = 68dBc (69dBFS)
ENOB = 11 BITS
SFDR = 72.4dB
SECOND HARMONIC
THIRD HARMONIC
Figure 21. AD9640-150 Single-Tone FFT with f
IN
= 337 MHz