Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- PRODUCT HIGHLIGHTS
- TABLE OF CONTENTS
- REVISION HISTORY
- GENERAL DESCRIPTION
- SPECIFICATIONS
- ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105
- ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ150
- ADC AC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105
- ADC AC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ 150
- DIGITAL SPECIFICATIONS
- SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ105
- SWITCHING SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ150
- TIMING SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
- EQUIVALENT CIRCUITS
- TYPICAL PERFORMANCE CHARACTERISTICS
- THEORY OF OPERATION
- ADC OVERRANGE AND GAIN CONTROL
- SIGNAL MONITOR
- BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
- CHANNEL/CHIP SYNCHRONIZATION
- SERIAL PORT INTERFACE (SPI)
- MEMORY MAP
- READING THE MEMORY MAP TABLE
- EXTERNAL MEMORY MAP
- MEMORY MAP REGISTER DESCRIPTION
- Sync Control (Register 0x100)
- Fast Detect Control (Register 0x104)
- Fine Upper Threshold (Register 0x106 and Register 0x107)
- Fine Lower Threshold (Register 0x108 and Register 0x109)
- Signal Monitor DC Correction Control (Register 0x10C)
- Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E)
- Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110)
- Signal Monitor SPORT Control (Register 0x111)
- Signal Monitor Control (Register 0x112)
- Signal Monitor Period (Register 0x113 to Register 0x115)
- Signal Monitor Result Channel A (Register 0x116 to Register 0x118)
- Signal Monitor Result Channel B (Register 0x119 to Register 0x11B)
- APPLICATIONS INFORMATION
- OUTLINE DIMENSIONS

AD9640
Rev. B | Page 22 of 52
120
100
80
60
40
20
0
–90 –80 –70 –60 –50 –40 –30 –20 –10
06547-061
INPUT AMPLITUDE (dBFS)
SNR/SFDR (dBc AND dBFS)
0
SFDR (dBFS)
SNR (dBFS)
SFDR (dBc)
SNR (dBc)
85dB REFERENCE LINE
Figure 28. AD9640-150 Single-Tone SNR/SFDR vs. Input Amplitude (A
IN
)
with f
IN
= 2.3 MHz
120
100
80
60
40
20
0
–90 –80 –70 –60 –50 –40 –30 –20 –10
06547-062
INPUT AMPLITUDE (dBFS)
SNR/SFDR (dBc AND dBFS)
0
SFDR (dBFS)
SNR (dBFS)
SFDR (dBc)
SNR (dBc)
85dB REFERENCE LINE
Figure 29. AD9640-150 Single-Tone SFDR vs. Input Amplitude with
f
IN
= 98.12 MHz
95
90
85
80
75
70
65
60
0
06547-087
INPUT FREQUENCY (MHz)
SNR/SFDR (dBc)
45050 100 150 200 250 300 350 400
SFDR = +25°C
SFDR = –40°C
SFDR = +85°C
SNR = –40°C
SNR = +25°C
SNR = +85°C
Figure 30. AD9640-150 Single-Tone SNR/SFDR vs.
Input Frequency (f
IN
) and Temperature with 2 V p-p Full Scale
95
90
85
80
75
70
65
60
0
06547-088
INPUT FREQUENCY (MHz)
SNR/SFDR (dBc)
45050 100 150 200 250 300 350 400
SFDR = +25°C
SFDR = –40°C
SFDR = +85°C
SNR = –40°C
SNR = +25°C
SNR = +85°C
Figure 31. AD9640-150 Single-Tone SNR/SFDR vs.
Input Frequency (f
IN
) and Temperature with 1 V p-p Full Scale
0.8
–1.0
–40
06547-098
TEMPERATURE (°C)
GAIN/OFFSET ERROR (%FSR)
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–200 20406080
GAIN
OFFSET
Figure 32. AD9640 Gain and Offset vs. Temperature
0
–100
–80
–60
–40
–20
–120
–90 –78 –66 –54 –42 –30 –18
06547-063
INPUT AMPLITUDE (dBFS)
SNR/SFDR (dBc AND dBFS)
–6
SFDR (dBFS)
IMD3 (dBFS)
SFDR (dBc)
IMD3 (dBc)
Figure 33. AD9640-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (A
IN
)
with f
IN1
= 29.1 MHz, f
IN2
= 32.1 MHz, f
S
= 150 MSPS