Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- PRODUCT HIGHLIGHTS
- TABLE OF CONTENTS
- REVISION HISTORY
- GENERAL DESCRIPTION
- SPECIFICATIONS
- ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105
- ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ150
- ADC AC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105
- ADC AC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ 150
- DIGITAL SPECIFICATIONS
- SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ105
- SWITCHING SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ150
- TIMING SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
- EQUIVALENT CIRCUITS
- TYPICAL PERFORMANCE CHARACTERISTICS
- THEORY OF OPERATION
- ADC OVERRANGE AND GAIN CONTROL
- SIGNAL MONITOR
- BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
- CHANNEL/CHIP SYNCHRONIZATION
- SERIAL PORT INTERFACE (SPI)
- MEMORY MAP
- READING THE MEMORY MAP TABLE
- EXTERNAL MEMORY MAP
- MEMORY MAP REGISTER DESCRIPTION
- Sync Control (Register 0x100)
- Fast Detect Control (Register 0x104)
- Fine Upper Threshold (Register 0x106 and Register 0x107)
- Fine Lower Threshold (Register 0x108 and Register 0x109)
- Signal Monitor DC Correction Control (Register 0x10C)
- Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E)
- Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110)
- Signal Monitor SPORT Control (Register 0x111)
- Signal Monitor Control (Register 0x112)
- Signal Monitor Period (Register 0x113 to Register 0x115)
- Signal Monitor Result Channel A (Register 0x116 to Register 0x118)
- Signal Monitor Result Channel B (Register 0x119 to Register 0x11B)
- APPLICATIONS INFORMATION
- OUTLINE DIMENSIONS

AD9640
Rev. B | Page 23 of 52
0
–100
–80
–60
–40
–20
–120
–90 –78 –66 –54 –42 –30 –18
06547-064
INPUT AMPLITUDE (dBFS)
SNR/SFDR (dBc AND dBFS)
–6
SFDR (dBFS)
SFDR (dBc)
IMD3 (dBc)
IMD3 (dBFS)
Figure 34. AD9640-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (A
IN
)
with f
IN1
= 169.1 MHz, f
IN2
= 172.1 MHz, f
S
= 150 MSPS
0 61.44
0
–120
06547-102
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
15.36 30.72 46.08
Figure 35. AD9640-125, Two 64 k WCDMA Carriers
with f
IN
= 170 MHz, f
S
= 122.88 MSPS
0 10 20 30 40 50 7060
0
–120
06547-065
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
150 MSPS
29.1MHz @–7dBFS
32.1MHz @–7dBFS
SFDR = 86.1dBc (93dBFS)
Figure 36. AD9640-150 Two-Tone FFT with f
IN1
= 29.1 MHz and f
IN2
= 32.1 MHz
0 10 20 30 40 50 7060
0
–120
06547-066
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
150 MSPS
169.1MHz @–7dBFS
172.1MHz @–7dBFS
SFDR = 83.8dBc (90.8dBFS)
Figure 37. AD9640-150 Two-Tone FFT with f
IN1
= 169.1 MHz and
f
IN2
= 172.1 MHz
0
–120
0
06547-100
FREQUENCY (MHz)
AMPLITUDE (dBFS)
62.5
–20
–40
–60
–80
–100
15.625 31.25 46.875
NPR = 64.7dBc
NOTCH @ 18.5MHz
NOTCH WIDTH = 3MHz
Figure 38. AD9640 Noise Power Ratio (NPR)
0 150
100
70
06547-067
CLOCK FREQUENCY (Msps)
SNR/SFDR (dBc)
95
90
85
80
75
25 50 75 100 125
SNR—SIDE A
SNR—SIDE B
SFDR—SIDE A
SFDR—SIDE B
Figure 39. AD9640-125 Single-Tone SNR/SFDR vs. Clock Frequency (f
S
)
with f
IN
= 2.3 MHz