Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- PRODUCT HIGHLIGHTS
- TABLE OF CONTENTS
- REVISION HISTORY
- GENERAL DESCRIPTION
- SPECIFICATIONS
- ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105
- ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ150
- ADC AC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105
- ADC AC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ 150
- DIGITAL SPECIFICATIONS
- SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ105
- SWITCHING SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ150
- TIMING SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
- EQUIVALENT CIRCUITS
- TYPICAL PERFORMANCE CHARACTERISTICS
- THEORY OF OPERATION
- ADC OVERRANGE AND GAIN CONTROL
- SIGNAL MONITOR
- BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
- CHANNEL/CHIP SYNCHRONIZATION
- SERIAL PORT INTERFACE (SPI)
- MEMORY MAP
- READING THE MEMORY MAP TABLE
- EXTERNAL MEMORY MAP
- MEMORY MAP REGISTER DESCRIPTION
- Sync Control (Register 0x100)
- Fast Detect Control (Register 0x104)
- Fine Upper Threshold (Register 0x106 and Register 0x107)
- Fine Lower Threshold (Register 0x108 and Register 0x109)
- Signal Monitor DC Correction Control (Register 0x10C)
- Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E)
- Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110)
- Signal Monitor SPORT Control (Register 0x111)
- Signal Monitor Control (Register 0x112)
- Signal Monitor Period (Register 0x113 to Register 0x115)
- Signal Monitor Result Channel A (Register 0x116 to Register 0x118)
- Signal Monitor Result Channel B (Register 0x119 to Register 0x11B)
- APPLICATIONS INFORMATION
- OUTLINE DIMENSIONS

AD9640
Rev. B | Page 24 of 52
10
0
N – 4
OUTPUT CODE
NUMBER OF HITS (1M)
8
6
4
2
N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4
1.3 LSB rms
06547-079
Figure 40. AD9640 Grounded Input Histogram
0 16,384
2.0
–2.0
–1.5
–1.0
–0.5
06547-068
OUTPUT CODE
INL ERROR (LSB)
8192
1.5
1.0
0.5
0
2048 4096 6144 10,240 12,288 14,336
Figure 41. AD9640 INL with f
IN
= 10.3 MHz
0 16,384
0.5
–0.5
–0.4.
–0.3
–0.2
–0.1
06547-069
OUTPUT CODE
DNL ERROR (LSB)
8192
0.4
0.3
0.2
0.1
0
2048 4096 6144 10,240 12,288 14,336
Figure 42. AD9640 DNL with f
IN
= 10.3 MHz
100
60
20 80
DUTY CYCLE (%)
SNR/SFDR (dBc)
SFDR DCS ON
SFDR DCS OFF
SNR DCS OFF
SNR DCS ON
95
90
85
80
75
70
65
40 60
06547-090
Figure 43. AD9640 SNR/SFDR vs. Duty Cycle with f
IN
= 10.3 MHz
90
70
0.5 1.3
INPUT COMMON-MODE VOLTAGE (V)
SNR/SFDR (dBc)
85
80
75
0.6 0.7 0.8 0.9 1.0 1.1 1.2
SFDR
SNR
06547-091
Figure 44. AD9640 SNR/SFDR vs. Input Common Mode Voltage (VCM)
with f
IN
= 30 MHz