Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- PRODUCT HIGHLIGHTS
- TABLE OF CONTENTS
- REVISION HISTORY
- GENERAL DESCRIPTION
- SPECIFICATIONS
- ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105
- ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ150
- ADC AC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105
- ADC AC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ 150
- DIGITAL SPECIFICATIONS
- SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ105
- SWITCHING SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ150
- TIMING SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
- EQUIVALENT CIRCUITS
- TYPICAL PERFORMANCE CHARACTERISTICS
- THEORY OF OPERATION
- ADC OVERRANGE AND GAIN CONTROL
- SIGNAL MONITOR
- BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
- CHANNEL/CHIP SYNCHRONIZATION
- SERIAL PORT INTERFACE (SPI)
- MEMORY MAP
- READING THE MEMORY MAP TABLE
- EXTERNAL MEMORY MAP
- MEMORY MAP REGISTER DESCRIPTION
- Sync Control (Register 0x100)
- Fast Detect Control (Register 0x104)
- Fine Upper Threshold (Register 0x106 and Register 0x107)
- Fine Lower Threshold (Register 0x108 and Register 0x109)
- Signal Monitor DC Correction Control (Register 0x10C)
- Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E)
- Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110)
- Signal Monitor SPORT Control (Register 0x111)
- Signal Monitor Control (Register 0x112)
- Signal Monitor Period (Register 0x113 to Register 0x115)
- Signal Monitor Result Channel A (Register 0x116 to Register 0x118)
- Signal Monitor Result Channel B (Register 0x119 to Register 0x11B)
- APPLICATIONS INFORMATION
- OUTLINE DIMENSIONS
AD9640
Rev. B | Page 45 of 52
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
0x10C
Signal Monitor
DC Correction
Control
(Global)
Open
DC
correction
freeze
DC Correction Bandwidth[3:0]
DC
correction
for signal
path
enable
DC
correction
for SM
enable
0x00
0x10D
Signal Monitor
DC Value
Channel A
Register 0
(Global)
DC Value Channel A[7:0] Read only
0x10E
Signal Monitor
DC Value
Channel A
Register 1
(Global)
Open Open DC Value Channel A[13:8] Read only
0x10F
Signal Monitor
DC Value
Channel B
Register 0
(Global)
DC Value Channel B[7:0] Read only
0x110
Signal Monitor
DC Value
Channel B
Register 1
(Global)
Open Open DC Value Channel B[13:8] Read only
0x111
Signal Monitor
SPORT Control
(Global)
Open
RMS/MS
magnitude
output
enable
Peak
power
output
enable
Threshold
crossing
output
enable
SPORT SMI
CLK divide
00 = undefined
01 = divide by 2
10 = divide by 4
11 = divide by 8
SPORT
SMI SCLK
sleep
Signal
monitor
SPORT
output
enable
0x04
0x112
Signal Monitor
Control
(Global)
Complex
power
calculation
mode
enable
Open Open Open
MS
mode
0 =
rms
1 = ms
Signal monitor mode
00 = RMS/MS Magnitude
01 = peak power
1x = threshold count
Signal
monitor
enable
0x00
0x113
Signal Monitor
Period
Register 0
(Global)
Signal Monitor Period[7:0] 0x40
In ADC clock
cycles
0x114
Signal Monitor
Period
Register 1
(Global)
Signal Monitor Period[15:8] 0x00
In ADC clock
cycles
0x115
Signal Monitor
Period
Register 2
(Global)
Signal Monitor Period[23:16] 0x00
In ADC clock
cycles
0x116
Signal Monitor
Result
Channel A
Register 0
(Global)
Signal Monitor Result Channel A[7:0] Read only
0x117
Signal Monitor
Result
Channel A
Register 1
(Global)
Signal Monitor Result Channel A[15:8] Read only
0x118
Signal Monitor
Result
Channel A
Register 2
(Global)
Open Open Open Open Signal Monitor Value Channel A[19:16] Read only
0x119
Signal Monitor
Result
Channel B
Register 0
(Global)
Signal Monitor Result Channel B[7:0] Read only