Datasheet

AD9640
Rev. B | Page 49 of 52
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design and layout of the AD9640 as a system,
it is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9640, it is recommended
that two separate 1.8 V supplies be used: one supply should be
used for analog (AVDD) and digital (DVDD), and a separate
supply should be used for the digital outputs (DRVDD). The
AVDD and DVDD supplies, while derived from the same
source, should be isolated with a ferrite bead or filter choke
and separate decoupling capacitors. The user can employ
several different decoupling capacitors to cover both high
and low frequencies. These should be located close to the
point of entry at the PC board level and close to the part’s
pins with minimal trace length.
A single PCB ground plane should be sufficient when using the
AD9640. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
LVDS Operation
The AD9640 defaults to CMOS output mode on power-up.
If LVDS operation is desired, this mode must be programmed
using the SPI configuration registers after power-up. When the
AD9640 powers up in CMOS mode with LVDS termination
resistors (100 Ω) on the outputs, the DRVDD current may be
higher than the typical value until the part is placed in LVDS
mode. This additional DRVDD current does not cause damage
to the AD9640, but it should be taken into account when consid-
ering the maximum DRVDD current for the part.
To avoid this additional DRVDD current, the AD9640 outputs
can be disabled at power-up by taking the OEB pin high. After
the part is placed into LVDS mode via the SPI port, the OEB
pin can be taken low to enable the outputs.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance. A continuous, exposed
(no solder mask), copper plane on the PCB should mate to the
AD9640 exposed paddle, Pin 0.
The copper plane should have several vias to achieve the lowest
possible resistive thermal path for heat dissipation to flow
through the bottom of the PCB. These vias should be filled or
plugged with nonconductive epoxy.
To maximize the coverage and adhesion between the ADC and
PCB, a silkscreen should be overlaid to partition the continuous
plane on the PCB into several uniform sections. This provides
several tie points between the two during the reflow process.
Using one continuous plane with no partitions guarantees only
one tie point between the ADC and PCB. See the evaluation
board for a PCB layout example. For detailed information about
packaging and PCB layout of chip scale packages, see the AN-772
Application Note, A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP).
CML
The CML pin should be decoupled to ground with a 0.1 F
capacitor, as shown in Figure 47.
RBIAS
The AD9640 requires that a 10 kΩ resistor be placed between
the RBIAS pin and ground. This resistor sets the master current
reference of the ADC core and should have at least a 1% tolerance.
Reference Decoupling
The VREF pin should be externally decoupled to ground with a
low ESR 1.0 F capacitor in parallel with a 0.1 F ceramic, low
ESR capacitor.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9640 to keep these signals from transitioning at the converter
inputs during critical sampling periods.