Datasheet

Data Sheet AD9653
Rev. 0 | Page 29 of 40
Two output clocks are provided to assist in capturing data from
the AD9653. The DCO is used to clock the output data and is
equal to four times the sample clock (CLK) rate for the default
mode of operation. Data is clocked out of the AD9653 and must
be captured on the rising and falling edges of the DCO that
supports double data rate (DDR) capturing. The FCO is used to
signal the start of a new output byte and is equal to the sample
clock rate in 1× frame mode. See the Timing Diagrams section
for more information.
When the SPI is used, the DCO phase can be adjusted in 60°
increments relative to the data edge. This enables the user to
refine system timing margins if required. The default DCO+
and DCO− timing, as shown in Figure 2, is 90° relative to the
output data edge.
In default mode, as shown in Figure 2, the MSB is first in the
data output serial stream. This can be inverted so that the LSB
is first in the data output serial stream by using the SPI.
There are 12 digital output test pattern options available that
can be initiated through the SPI. This is a useful feature when
validating receiver capture and timing. Refer to Table 13 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various
ways, depending on the test pattern chosen. Note that some
patterns do not adhere to the data format select option. In
addition, custom user-defined test patterns can be assigned in
the 0x19, 0x1A, 0x1B, and 0x1C register addresses.
Table 12. Digital Output Coding
Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode
VIN+ − VIN− <−VREF − 0.5 LSB 0000 0000 0000 0000 1000 0000 0000 0000
VIN+ − VIN− −VREF 0000 0000 0000 0000 1000 0000 0000 0000
VIN+ − VIN− 0 V 1000 0000 0000 0000 0000 0000 0000 0000
VIN+ − VIN− +VREF − 1.0 LSB 1111 1111 1111 1111 0111 1111 1111 1111
VIN+ − VIN− >+VREF − 0.5 LSB 1111 1111 1111 1111 0111 1111 1111 1111
Table 13. Flexible Output Test Modes
Output Test
Mode Bit
Sequence Pattern Name Digital Output Word 1 Digital Output Word 2
Subject to
Data Format
Select Notes
0000 Off (default) N/A N/A N/A
0001
Midscale short
1000 0000 0000 0000 (16-bit)
N/A
Yes
Offset binary
code shown
0010 +Full-scale short 0000 0000 0000 0000 (16-bit) N/A Yes Offset binary
code shown
0011 −Full-scale short 0000 0000 0000 0000 (16-bit) N/A Yes Offset binary
code shown
0100 Checkerboard 1010 1010 1010 1010 (16-bit) 0101 0101 0101 0100 (16-bit) No
0101 PN sequence long N/A N/A Yes PN23
ITU 0.150
X
23
+ X
18
+ 1
0110 PN sequence short N/A N/A Yes PN9
ITU 0.150
X
9
+ X
5
+ 1
0111 One-/zero-word
toggle
111 1111 1111 1100 (16-bit) 0000 0000 0000 0000 (16-bit) No
1000 User input Register 0x19 to Register 0x1A Register 0x1B to Register 0x1C No
1001 1-/0-bit toggle 1010 1010 1010 1000 (16-bit) N/A No
1010
1× sync
0000 0001 1111 1100 (16-bit)
N/A
No
1011 One bit high 1000 0000 0000 0000 (16-bit) N/A No Pattern
associated with
the external pin
1100 Mixed frequency 1010 0001 1001 1100 (16-bit) N/A No