Datasheet

Data Sheet AD9653
Rev. 0 | Page 9 of 40
TIMING SPECIFICATIONS
Table 7.
Parameter Description Limit
Unit
SYNC TIMING REQUIREMENTS
t
SSYNC
SYNC to rising edge of CLK+ setup time 0.24 ns typ
t
HSYNC
SYNC to rising edge of CLK+ hold time 0.40 ns typ
SPI TIMING REQUIREMENTS See Figure 75
t
DS
Setup time between the data and the rising edge of SCLK 2 ns min
t
DH
Hold time between the data and the rising edge of SCLK 2 ns min
t
CLK
Period of the SCLK 40 ns min
t
S
Setup time between CSB and SCLK 2 ns min
t
H
Hold time between CSB and SCLK 2 ns min
t
HIGH
SCLK pulse width high 10 ns min
t
LOW
SCLK pulse width low 10 ns min
t
EN_SDIO
Time required for the SDIO pin to switch from an input to an output relative to the
SCLK falling edge (not shown in Figure 75)
10 ns min
t
DIS_SDIO
Time required for the SDIO pin to switch from an output to an input relative to the
SCLK rising edge (not shown in Figure 75)
10 ns min
Timing Diagrams
Refer to the Memory Map Register Descriptions section and Table 23 for SPI register settings.
Figure 2. 16-Bit DDR/SDR, Two-Lane, 1× Frame Mode (Default)
D0–A
D0+A
D1–A
D1+A
FCO–
BYTEWISE
MODE
FCO+
D0–A
D0+A
D1–A
D1+A
FCO–
DCO
DCO+
CLK+
VIN±x
CLK–
DCO–
FCO+
BITWISE
MODE
SDR
DDR
10538-002
MSB
N – 17
D14
N – 17
D13
N – 17
D12
N – 17
D11
N – 17
D10
N – 17
D09
N – 17
D08
N – 17
MSB
N – 16
D14
N – 16
D13
N – 16
D12
N – 16
D11
N – 16
D10
N – 16
D09
N – 16
D08
N – 16
D07
N – 17
D06
N – 17
D05
N – 17
D04
N – 17
D03
N – 17
D02
N – 17
D01
N – 17
LSB
N – 17
D07
N – 16
D06
N – 16
D05
N – 16
D04
N – 16
D03
N – 16
D02
N – 16
D01
N – 16
LSB
N – 16
MSB
N – 17
D13
N – 17
D11
N – 17
D09
N – 17
D07
N – 17
D05
N – 17
D03
N – 17
D01
N – 17
MSB
N – 16
D13
N – 16
D11
N – 16
D09
N – 16
D07
N – 16
D05
N – 16
D03
N – 16
D01
N – 16
D14
N – 17
D12
N – 17
D10
N – 17
D08
N – 17
D06
N – 17
D04
N – 17
D02
N – 17
LSB
N – 17
D14
N – 16
D12
N – 16
D10
N – 16
D08
N – 16
D06
N – 16
D04
N – 16
D02
N – 16
LSB
N – 16
t
A
t
DATA
t
LD
t
EH
t
FCO
t
FRAME
t
PD
t
CPD
t
EL
N – 1
N
N + 1