Datasheet

AD9709
Rev. B | Page 20 of 32
SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT
Figure 39 shows the AD9709 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly terminated
50 Ω cable, because the nominal full-scale current, I
OUTFS
, of 20 mA
flows through the equivalent R
LOAD
of 25 Ω. In this case, R
LOAD
represents the equivalent load resistance seen by I
OUTA
or I
OUTB
.
The unused output (I
OUTA
or I
OUTB
) can be connected directly to
ACOM or via a matching R
LOAD
. Different values of I
OUTFS
and
R
LOAD
can be selected as long as the positive compliance range is
adhered to. One additional consideration in this mode is the
INL (see the Analog Outputs section). For optimum INL
performance, the single-ended, buffered voltage output
configuration is suggested.
AD9709
50Ω
25Ω
50Ω
V
OUTA
= 0V TO 0.5V
I
OUTFS
= 20mA
I
OUTA
I
OUTB
00606-038
Figure 39. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 40 shows a buffered single-ended output configuration
in which the U1 op amp performs an I-V conversion on the
AD9709 output current. U1 maintains I
OUTA
(or I
OUTB
) at a
virtual ground, thus minimizing the nonlinear output
impedance effect on the INL performance of the DAC, as
discussed in the Analog Outputs section. Although this single-
ended configuration typically provides the best dc linearity
performance, its ac distortion performance at higher DAC
update rates may be limited by the slewing capabilities of U1.
U1 provides a negative unipolar output voltage, and its full-
scale output voltage is simply the product of R
FB
and I
OUTFS
. The
full-scale output should be set within U1’s voltage output swing
capabilities by scaling I
OUTFS
and/or R
FB
. An improvement in ac
distortion performance may result with a reduced I
OUTFS
because
the signal current U1 has to sink will be subsequently reduced.
AD9709
I
OUTFS
= 10mA
U1
I
OUTA
I
OUTB
V
OUT
= I
OUTFS
× R
FB
C
OPT
200Ω
R
FB
200Ω
00606-039
Figure 40. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS
Power Supply Rejection
Many applications seek high speed and high performance under
less than ideal operating conditions. In these applications, the
implementation and construction of the printed circuit board is
as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing as well as
power supply bypassing and grounding to ensure optimum
performance. Figure 52 and Figure 53 illustrate the recommended
circuit board layout, including ground, power, and signal
input/output.
One factor that can measurably affect system performance is
the ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated with
the DAC’s full-scale current, I
OUTFS
. AC noise on the dc supplies
is common in applications where the power distribution is
generated by a switching power supply. Typically, switching
power supply noise occurs over the spectrum from tens of
kilohertz to several megahertz. The PSRR vs. frequency of the
AD9709 AVDD supply over this frequency range is shown in
Figure 41.
90
70
85
80
75
PSRR (dB)
0.20.30.40.50.60.70.80.91.01.1
FREQUENCY (MHz)
00606-040
Figure 41. AVDD Power Supply Rejection Ratio vs. Frequency
Note that the data in Figure 41 is given in terms of current out
vs. voltage in. Noise on the analog power supply has the effect
of modulating the internal current sources and therefore the
output current. The voltage noise on AVDD, therefore, is added
in a nonlinear manner to the desired I
OUT
. PSRR is very code
dependent, thus producing mixing effects that can modulate
low frequency power supply noise to higher frequencies. Worst-
case PSRR for either one of the differential DAC outputs occurs
when the full-scale current is directed toward that output. As a
result, the PSRR measurement in Figure 41 represents a worst-
case condition in which the digital inputs remain static and the
full-scale output current of 20 mA is directed to the DAC
output being measured.