Datasheet

AD9709
Rev. B | Page 25 of 32
00606-147
OUT
DVDD
1K
U2
U2
JP2
DCLKIN2
DVDD
CC0805CC0805
CLK
CLR
PRE
Q
Q_
J K
DVDD
14
10
9 712
13 11
U6
SN74F112
DVDD;16
DGND;8
.1UF C7
.01UF
C8
RC0805
RC0805
RC0805
RC0805
JP16
JP5
JP4
JP3
R4 5050
R1
JP17
50 R13
R3 50
R2 50
DVDD DVDD
CC0805
CC0805
RC0603RC0603 RC0603
T1-1TCUP
RC0603
1KR17 R18 1K
R16
1K
R19
C19
.1
C18
.1
RC0805
SMA 200UP SMA 200UP SMA 200UP SMA 200UP
RC0603
W
RT2IN
IQSEL
RESET
CLK2IN
1QCLK
CLK1IN
IQWRT
W
RT1IN
SLEEP
R63 50
JP13
1 2 34
5 6
T3
S4
DGND;3,4,5
S3
DGND;3,4,5
S2
DGND;3,4,5
S1
DGND;3,4,5
WHT
WHT
WHT
WHT
JP14
WHT
DS90LV048B
SO16
+IN -IN
OUT
JP9
DCLKIN1
1 2
15
U2
7 8
DS90LV048B
SO16
+IN -IN
OUT OUT
CC0805
CC0805
DVDD
C34
.01UF
C33 .1UF
10
A
B
C
1
3
CLK
CLR
PRE
Q
Q_
J
K
2
SW1
3 1 26
5
4
U6
15
SN74F112
A
B
C
2
/2 CLOCK DIVIDER
CLK2
3
1
SW2
DVDD
WRT1 WRT2
DVDD;16
DGND;8
CLK1
SLEEP
JP1
DVDD
RC0603
12 13
DS90LV048B
EN
GND
VCC
EN
DS90LV048B
SO16
+IN -IN
DS90LV048B
SO16
+IN -IN
VAL R30
DVDD
3
14
4 5
11
6
U2
16
9
SO16
U2
Figure 47. Power Decoupling and Clocks on AD9709 Evaluation Board (2)