Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) LFCSP 40 VQ

Dual, Low Power, 8-/10-/12-/14-Bit

TxDAC

Digital-to-Analog Converters

AD9714/AD9715/AD9716/AD9717

Rev. A

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FEATURES

Power dissipation @ 3.3 V, 2 mA output

37 mW @ 10 MSPS

86 mW @ 125 MSPS

Sleep mode: <3 mW @ 3.3 V

Supply voltage: 1.8 V to 3.3 V

SFDR to Nyquist

84 dBc @ 1 MHz output

75 dBc @ 10 MHz output

AD9717 NSD @ 1 MHz output, 125 MSPS, 2 mA: −151 dBc/Hz

Differential current outputs: 1 mA to 4 mA

2 on-chip auxiliary DACs

CMOS inputs with single-port operation

Output common mode: adjustable 0 V to 1.2 V

Small footprint 40-lead LFCSP RoHS-compliant package

APPLICATIONS

Wireless infrastructures

Picocell, femtocell base stations

Medical instrumentation

Ultrasound transducer excitation

Portable instrumentation

Signal generators, arbitrary waveform generators

GENERAL DESCRIPTION

The AD9714/AD9715/AD9716/AD9717 are pin-compatible,

dual, 8-/10-/12-/14-bit, low power digital-to-analog converters

(DACs) that provide a sample rate of 125 MSPS. These TxDAC®

converters are optimized for the transmit signal path of commu-

nication systems. All the devices share the same interface, package,

and pinout, providing an upward or downward component

selection path based on performance, resolution, and cost.

The AD9714/AD9715/AD9716/AD9717 offer exceptional ac and

dc performance and support update rates up to 125 MSPS.

The flexible power supply operating range of 1.8 V to 3.3 V and

low power dissipation of the AD9714/AD9715/AD9716/AD9717

make them well-suited for portable and low power applications.

PRODUCT HIGHLIGHTS

1. Low Power.

DACs operate on a single 1.8 V to 3.3 V supply; total power

consumption reduces to 35 mW at 125 MSPS with a 1.8 V

supply. Sleep and power-down modes are provided for low

power idle periods.

2. CMOS Clock Input.

High speed, single-ended CMOS clock input supports a

125 MSPS conversion rate.

3. Easy Interfacing to Other Components.

Adjustable output common mode from 0 V to 1.2 V allows

easy interfacing to other components that accept common-

mode levels greater than 0 V.

Summary of content (80 pages)

PAGE 1
Dual, Low Power, 8-/10-/12-/14-Bit TxDAC Digital-to-Analog Converters AD9714/AD9715/AD9716/AD9717 FEATURES GENERAL DESCRIPTION Power dissipation @ 3.3 V, 2 mA output 37 mW @ 10 MSPS 86 mW @ 125 MSPS Sleep mode: <3 mW @ 3.3 V Supply voltage: 1.8 V to 3.
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AD9714/AD9715/AD9716/AD9717 TABLE OF CONTENTS Features .............................................................................................. 1 Estimating the Overall DAC Pipeline Delay........................... 42 Applications ....................................................................................... 1 Reference Operation .................................................................. 43 General Description .......................................................................
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AD9714/AD9715/AD9716/AD9717 REVISION HISTORY 3/09—Rev. 0 to Rev. A Changes to Figure 1........................................................................... 4 Changed DVDD = 3.3 V to DVDD = 1.8 V, Table 1 Conditions ............................................................................ 5 Changes to Table 1 ............................................................................ 5 Changed DVDD = 3.3 V to DVDD = 1.8 V, Table 2 Conditions .........................................................
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AD9714/AD9715/AD9716/AD9717 AD9717 1V SPI INTERFACE DB11 QRSET 16kΩ DB10 CMLI FSADJI/AUXI FSADJQ/AUXQ REFIO RESET/PINMD SCLK/CLKMD SDIO/FORMAT CS/PWRDN DB13 (MSB) DB12 FUNCTIONAL BLOCK DIAGRAM IRSET 16kΩ 10kΩ DB9 IREF 100µA DB8 IOUTN IOUTP 500Ω RLIP AUX1DAC AVDD 1 INTO 2 INTERLEAVED DATA INTERFACE DVSS RLIN 500Ω I DAC BAND GAP DVDDIO IRCML 1kΩ TO 250Ω AVSS AUX2DAC I DATA RLQP 500Ω 1.
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AD9714/AD9715/AD9716/AD9717 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 2 mA, maximum sample rate, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY, AVDD = DVDDIO = CVDD = 3.3 V Differential Nonlinearity (DNL) Precalibration Postcalibration Integral Nonlinearity (INL) Precalibration Postcalibration ACCURACY, AVDD = DVDDIO = CVDD = 1.
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AD9714/AD9715/AD9716/AD9717 Parameter REFERENCE INPUT Voltage Compliance AVDD = 3.3 V AVDD = 1.8 V Input Resistance External Reference Mode DAC MATCHING Gain Matching ANALOG SUPPLY VOLTAGES AVDD CVDD DIGITAL SUPPLY VOLTAGES DVDD DVDDIO POWER CONSUMPTION, AVDD = DVDDIO = CVDD = 3.3 V fDAC = 125 MSPS, IF = 12.5 MHz IAVDD IDVDD + IDVDDIO ICVDD Power-Down Mode with Clock Power-Down Mode, No Clock Power Supply Rejection Ratio POWER CONSUMPTION, AVDD = DVDDIO = CVDD = 1.8 V. fDAC = 125 MSPS, IF = 12.
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AD9714/AD9715/AD9716/AD9717 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 2 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter DAC CLOCK INPUT (CLKIN) VIH VIL Maximum Clock Rate SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) Minimum Pulse Width High Minimum Pulse Width Low INPUT DATA 1.8 V Q Channel or DCLKIO Falling Edge Setup Hold 1.8 V I Channel or DCLKIO Rising Edge Setup Hold 3.
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AD9714/AD9715/AD9716/AD9717 AC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 2 mA, maximum sample rate, unless otherwise noted. Table 3.
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AD9714/AD9715/AD9716/AD9717 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter AVDD, DVDDIO, CVDD to AVSS, DVSS, CVSS DVDD to DVSS AVSS to DVSS, CVSS DVSS to AVSS, CVSS CVSS to AVSS, DVSS REFIO, FSADJQ, FSADJI, CMLQ, CMLI to AVSS QOUTP, QOUTN, IOUTP, IOUTN, RLQP, RLQN, RLIP, RLIN to AVSS DBn1 (MSB) to DB0 (LSB), CS, SCLK, SDIO, RESET to DVSS CLKIN to CVSS Junction Temperature Storage Temperature Range 1 Rating −0.3 V to +3.9 V −0.3 V to +2.1 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to AVDD + 0.
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AD9714/AD9715/AD9716/AD9717 40 39 38 37 36 35 34 33 32 31 DB6 DB7 (MSB) CS/PWRDN SDIO/FORMAT SCLK/CLKMD RESET/PINMD REFIO FSADJI/AUXI FSADJQ/AUXQ CMLI PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR AD9714 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 RLIN IOUTN IOUTP RLIP AVDD AVSS RLQP QOUTP QOUTN RLQN NOTES 1. NC = NO CONNECT 2. THE EXPOSED PAD IS CONNECTED TO AVSS AND SHOULD BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD.
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AD9714/AD9715/AD9716/AD9717 Pin No. 31 Mnemonic CMLI 32 FSADJQ/AUXQ 33 FSADJI/AUXI 34 REFIO 35 RESET/PINMD 36 SCLK/CLKMD 37 SDIO/FORMAT 38 CS/PWRDN 39 40 41 (EPAD) DB7 (MSB) DB6 Exposed Pad (EPAD) Description I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected.
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40 39 38 37 36 35 34 33 32 31 DB8 DB9 (MSB) CS/PWRDN SDIO/FORMAT SCLK/CLKMD RESET/PINMD REFIO FSADJI/AUXI FSADJQ/AUXQ CMLI AD9714/AD9715/AD9716/AD9717 PIN 1 INDICATOR AD9715 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 RLIN IOUTN IOUTP RLIP AVDD AVSS RLQP QOUTP QOUTN RLQN NOTES 1. NC = NO CONNECT 2. THE EXPOSED PAD IS CONNECTED TO AVSS AND SHOULD BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD.
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AD9714/AD9715/AD9716/AD9717 Pin No. 31 Mnemonic CMLI 32 FSADJQ/AUXQ 33 FSADJI/AUXI 34 REFIO 35 RESET/PINMD 36 SCLK/CLKMD 37 SDIO/FORMAT 38 CS/PWRDN 39 40 41 (EPAD) DB9 (MSB) DB8 Exposed Pad (EPAD) Description I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected.
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40 39 38 37 36 35 34 33 32 31 DB10 DB11 (MSB) CS/PWRDN SDIO/FORMAT SCLK/CLKMD RESET/PINMD REFIO FSADJI/AUXI FSADJQ/AUXQ CMLI AD9714/AD9715/AD9716/AD9717 PIN 1 INDICATOR AD9716 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 RLIN IOUTN IOUTP RLIP AVDD AVSS RLQP QOUTP QOUTN RLQN NOTES 1. NC = NO CONNECT 2. THE EXPOSED PAD IS CONNECTED TO AVSS AND SHOULD BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD.
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AD9714/AD9715/AD9716/AD9717 Pin No. 31 Mnemonic CMLI 32 FSADJQ/AUXQ 33 FSADJI/AUXI 34 REFIO 35 RESET/PINMD 36 SCLK/CLKMD 37 SDIO/FORMAT 38 CS/PWRDN 39 40 41 (EPAD) DB11 (MSB) DB10 Exposed Pad (EPAD) Description I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected.
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40 39 38 37 36 35 34 33 32 31 DB12 DB13 (MSB) CS/PWRDN SDIO/FORMAT SCLK/CLKMD RESET/PINMD REFIO FSADJI/AUXI FSADJQ/AUXQ CMLI AD9714/AD9715/AD9716/AD9717 PIN 1 INDICATOR AD9717 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 RLIN IOUTN IOUTP RLIP AVDD AVSS RLQP QOUTP QOUTN RLQN NOTES 1. THE EXPOSED PAD IS CONNECTED TO AVSS AND SHOULD BE SOLDERED TO THE GROUND PLANE. EXPOSED METAL AT PACKAGE CORNERS IS CONNECTED TO THIS PAD.
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AD9714/AD9715/AD9716/AD9717 Pin No. 31 Mnemonic CMLI 32 FSADJQ/AUXQ 33 FSADJI/AUXI 34 REFIO 35 RESET/PINMD 36 SCLK/CLKMD 37 SDIO/FORMAT 38 CS/PWRDN 39 40 41 (EPAD) DB13 (MSB) DB12 Exposed Pad (EPAD) Description I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected.
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AD9714/AD9715/AD9716/AD9717 TYPICAL PERFORMANCE CHARACTERISTICS 1.5 1.5 1.0 1.0 POSTCALIBRATION INL (LSB) 0.5 0 –0.5 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE –1.5 1.0 1.0 POSTCALIBRATION DNL (LSB) PRECALIBRATION DNL (LSB) 1.5 0.5 0 –0.5 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE Figure 7. AD9717 Precalibration DNL at 1.8 V (DVDD = 1.8 V) 6144 8192 10,240 12,288 14,336 16,384 CODE 0 –0.5 –1.
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1.75 1.75 1.25 1.25 POSTCALIBRATION DNL (LSB) 0.75 0.25 –0.25 –0.75 –0.25 –0.75 –1.25 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE –1.75 07265-010 0 0.4 0.4 0.3 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 0 512 1024 1536 2048 CODE 2560 3072 3584 4096 0.1 0 –0.1 –0.2 –0.4 0 512 1024 1536 2048 CODE 2560 3072 3584 4096 Figure 16. AD9716 Postcalibration INL at 1.8 V 0.4 0.3 0.3 POSTCALIBRATION DNL (LSB) 0.4 0.2 0.1 0 –0.1 –0.2 –0.3 0.2 0.1 0 –0.1 –0.2 –0.
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0.4 0.4 0.3 0.3 POSTCALIBRATION INL (LSB) 0.2 0.1 0 –0.1 –0.2 0 –0.1 –0.2 –0.3 0 512 1024 1536 2048 CODE 2560 3072 3584 4096 –0.4 07265-016 0 0.4 0.4 0.3 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 2048 CODE 2560 3072 3584 4096 0.2 0.1 0 –0.1 –0.2 0 512 1024 1536 2048 CODE 2560 3072 3584 4096 –0.4 0 Figure 19. AD9716 Precalibration DNL at 3.3 V 1024 1536 2048 CODE 2560 3072 3584 4096 0.13 0.08 POSTCALIBRATION INL (LSB) 0.08 0.03 –0.
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0.13 0.08 0.08 0.03 –0.02 –0.07 128 256 384 512 CODE 640 768 896 1024 –0.07 –0.12 0 0.13 0.08 0.08 POSTCALIBRATION INL (LSB) 0.13 0.03 –0.02 –0.07 –0.12 0 128 256 384 512 CODE 640 768 896 1024 –0.12 POSTCALIBRATION DNL (LSB) 0.03 –0.02 –0.07 512 CODE 640 768 896 1024 07265-024 PRECALIBRATION DNL (LSB) 0.08 384 768 896 1024 0 128 256 384 512 CODE 640 768 896 1024 Figure 28. AD9715 Postcalibration INL at 3.3 V 0.08 256 640 –0.07 0.
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0.025 0.025 0.020 0.020 0.015 0.015 POSTCALIBRATION INL (LSB) 0.010 0.005 0 –0.005 –0.010 –0.015 0 –0.005 –0.010 –0.015 –0.020 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 CODE –0.025 07265-028 0 Figure 33. AD9714 Postcalibration INL at 1.8 V 0.025 0.025 0.020 0.020 0.015 0.015 POSTCALIBRATION DNL (LSB) PRECALIBRATION DNL (LSB) Figure 30. AD9714 Precalibration INL at 1.8 V 0.010 0.005 0 –0.005 –0.010 –0.015 –0.020 0.010 0.005 0 –0.005 –0.010 –0.015 –0.
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0.025 0.025 0.020 0.020 0.015 0.015 POSTCALIBRATION DNL (LSB) 0.010 0.005 0 –0.005 –0.010 –0.015 –0.020 0.005 0 –0.005 –0.010 –0.015 –0.020 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 CODE –0.025 07265-034 –0.025 0.010 0 Figure 36. AD9714 Precalibration DNL at 3.3 V 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 CODE 07265-037 PRECALIBRATION DNL (LSB) AD9714/AD9715/AD9716/AD9717 Figure 39. AD9714 Postcalibration DNL at 3.
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AD9714/AD9715/AD9716/AD9717 –130 –130 –133 –133 –136 –136 –139 –139 NSD (dBc) 1.8V, 2mA –145 –145 –148 –151 –151 –154 –154 07265-142 –148 –157 0 5 10 15 20 25 30 35 40 45 50 3.3V, 1mA –142 –157 55 0 5 10 15 25 30 35 40 45 50 55 Figure 45. AD9717 Noise Spectral Density at Three Output Currents, 3.3 V –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 (dBm) (dBm) Figure 42. AD9717 Noise Spectral Density at Two Output Currents, 1.
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AD9714/AD9715/AD9716/AD9717 90 90 +85°C 84 84 +25°C +25°C 78 IMD (dBc) 72 –40°C 72 66 66 60 60 54 5 10 15 20 25 30 35 40 45 07265-151 +85°C –40°C 07265-148 54 5 50 10 15 20 Figure 48. AD9717 IMD at Three Temperatures, 1.8 V 35 40 45 50 91 82 88 76 0dB –3dB –3dB IMD (dBc) IMD (dBc) 30 Figure 51. AD9717 IMD at Three Temperatures, 3.
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–10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –80 –80 –90 –90 –100 –100 –110 START 1MHz 1.5MHz/DIV STOP 16MHz 07265-084 –70 –110 START 1MHz Figure 54. AD9717 Single-Tone Spectrum, 1.8 V STOP 15MHz Figure 57. AD9717 Single-Tone Spectrum, 3.3 V 86 93 AD9717 AD9716 AD9715 AD9714 80 AD9717 AD9716 AD9715 AD9714 90 87 74 84 SFDR (dBc) SFDR (dBc) 1.
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AD9714/AD9715/AD9716/AD9717 90 90 85 85 –6dB 80 80 –6dB 0dB –3dB 65 70 60 60 55 55 0 10 20 30 fIN (MHz) 40 50 50 07265-092 50 60 –3dB 65 0dB 0 10 20 30 40 50 07265-091 70 75 SFDR (dBc) SFDR (dBc) 75 60 fIN (MHz) Figure 60. SFDR at Three Digital Input Levels vs. fIN, 1.8 V Figure 63. SFDR at Three Digital Input Levels vs. fIN, 3.
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AD9714/AD9715/AD9716/AD9717 –60 –60 1mA PRECAL 1mA PRECAL –65 1mA POSTCAL 2mA POSTCAL ACLR (dBc) ACLR (dBc) –65 2mA POSTCAL 1mA POSTCAL –70 2mA PRECAL –70 4mA POSTCAL –75 2mA PRECAL 35 45 fOUT (MHz) 07265-068 25 –80 15 25 35 45 fOUT (MHz) Figure 66. AD9717 One-Carrier W-CDMA First ACLR, 1.8 V 07265-070 4mA PRECAL –75 15 Figure 69. AD9717 One-Carrier W-CDMA First ACLR, 3.
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AD9714/AD9715/AD9716/AD9717 AC-COUPLED:UNSPECIFIED BELOW 20MHz 10dB/DIV 10dB/DIV AC-COUPLED: UNSPECIFIED BELOW 20MHz SPAN 38.84MHz VBW 300kHz CENTER 22.90MHz SWEEP 126ms (601pts) TOTAL CARRIER POWER –23.08dBm/7.87420MHz REF CARRIER POWER –25.84dBm/4.03420MHz RCC FILTER: OFF FILTER ALPHA 0.22 SWEEP 126ms (601pts) TOTAL CARRIER POWER –33.14dBm/7.87420MHz REF CARRIER POWER –25.86dBm/4.03420MHz RCC FILTER: OFF FILTER ALPHA 0.22 OFFSET INTEG LOWER UPPER dBc dBm dBc dBm FREQ BW 1. –25.86dBm 5.000MHz 3.
PAGE 30
AD9714/AD9715/AD9716/AD9717 –55 –55 1mA PRECAL 1mA PRECAL –60 1mA POSTCAL ACLR (dBc) ACLR (dBc) –60 2mA PRECAL 1mA POSTCAL 2mA PRECAL –65 –65 2mA POSTCAL –70 2mA POSTCAL 30 35 40 fOUT (MHz) 07265-078 25 –75 20 35 40 Figure 81. AD9717 Two-Carrier W-CDMA Third ACLR, 3.3 V 0.4 1.0 0.3 0.8 0.2 0.6 0.1 0.4 AUXDAC INL (LSB) 0 –0.1 –0.2 –0.3 0.2 0 –0.2 –0.4 –0.6 –0.4 0 128 256 384 512 CODE 640 768 896 07265-147 –0.8 1024 –1.
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AD9714/AD9715/AD9716/AD9717 TERMINOLOGY Linearity Error or Integral Nonlinearity (INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Power Supply Rejection Power supply rejection is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages.
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AD9714/AD9715/AD9716/AD9717 CMLI FSADJI/AUXI FSADJQ/AUXQ REFIO RESET/PINMD SCLK/CLKMD SDIO/FORMAT CS/PWRDN DB13 (MSB) DB12 THEORY OF OPERATION 1V SPI INTERFACE DB11 AD9717 QRSET 16kΩ DB10 IRSET 16kΩ 10kΩ DB9 IREF 100µA DB8 IOUTN IOUTP 500Ω RLIP AUX1DAC AVDD 1 INTO 2 INTERLEAVED DATA INTERFACE DVSS RLIN 500Ω I DAC BAND GAP DVDDIO IRCML 1kΩ TO 250Ω AVSS AUX2DAC I DATA RLQP 500Ω 1.
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AD9714/AD9715/AD9716/AD9717 SERIAL PERIPHERAL INTERFACE (SPI) The serial port of the AD9714/AD9715/AD9716/AD9717 is a flexible, synchronous serial communications port that allows easy interfacing to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel® SSR protocols. The interface allows read/write access to all registers that configure the AD9714/AD9715/AD9716/AD9717.
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AD9714/AD9715/AD9716/AD9717 MSB/LSB TRANSFERS INSTRUCTION CYCLE When LSBFIRST = 1 (LSB first), the instruction and data bytes must be written from the least significant bit to the most significant bit. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. The serial port internal byte address generator increments for each byte of the multibyte communication cycle.
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AD9714/AD9715/AD9716/AD9717 SPI REGISTER MAP Table 13.
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AD9714/AD9715/AD9716/AD9717 SPI REGISTER DESCRIPTIONS Reading these registers returns previously written values for all defined register bits, unless otherwise noted. Table 14.
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AD9714/AD9715/AD9716/AD9717 Register IRSET IRCML Address 0x04 0x05 Bit 7 Name IRSETEN 5:0 IRSET[5:0] 7 IRCMLEN 5:0 IRCML[5:0] Q DAC Gain 0x06 5:0 Q DACGAIN[5:0] QRSET 0x07 7 QRSETEN 5:0 QRSET[5:0] 7 QRCMLEN 5:0 QRCML[5:0] QRCML 0x08 AUXDAC Q 0x09 7:0 QAUXDAC[7:0] AUX CTLQ 0x0A 7 QAUXEN 6:5 QAUXRNG[1:0] 4:2 QAUXOFS[2:0] 1:0 QAUXDAC[9:8] Description 0 (default): IRSET resistor value for I channel is set by an external resistor connected to the FADJI/AUXI pin.
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AD9714/AD9715/AD9716/AD9717 Register AUXDAC I Address 0x0B Bit 7:0 Name IAUXDAC[7:0] AUX CTLI 0x0C 7 IAUXEN 6:5 IAUXRNG[1:0] 4:2 IAUXOFS[2:0] Reference Resistor 0x0D 1:0 5:0 IAUXDAC[9:8] RREF[5:0] Cal Control 0x0E 7 PRELDQ 6 PRELDI 5 CALSELQ 4 CALSELI 3 CALCLK 2:0 DIVSEL[2:0] 7 CALSTATQ 6 CALSTATI 3:2 CALMEMQ[1:0] 1:0 CALMEMI[1:0] 5:0 5:0 MEMADDR[5:0] MEMDATA[5:0] Cal Memory Memory Address Memory Data 0x0F 0x10 0x11 Description AUXDAC I output voltage adjustment w
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AD9714/AD9715/AD9716/AD9717 Register Memory R/W CLKMODE Version Address 0x12 0x14 0x1F Bit 7 Name CALRSTQ 6 CALRSTI 4 CALEN 3 SMEMWR 2 SMEMRD 1 UNCALQ 0 UNCALI 7:6 CLKMODEQ[1:0] 4 Searching 3 2 Reacquire CLKMODEN 1:0 CLKMODEI[1:0] 7:0 Version[7:0] Description 0 (default): no action. 1: clear CALSTATQ. 0 (default): no action. 1: clear CALSTATI. 0 (default): no action. 1: initiate device self-calibration. 0 (default): no action.
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AD9714/AD9715/AD9716/AD9717 DIGITAL INTERFACE OPERATION Digital data for the I and Q DACs is supplied over a single parallel bus (DB[n:0), where n is 7 for the AD9714, 9 for the AD9715, 11 for the AD9716, and 13 for the AD9717) accompanied by a qualifying clock (DCLKIO). The I and Q data are provided to the chip in an interleaved double data rate (DDR) format. The maximum guaranteed data rate is 250 MSPS with a 125 MHz clock.
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AD9714/AD9715/AD9716/AD9717 OR DB[n:0] (INPUT) RETIMER-CLK D-FF D-FF D-FF D-FF 0 1 2 3 D-FF TO DAC CORE IOUT CLKIN-INT IOUT NOTES D-FFs: 0: RISING OR FALLING EDGE TRIGGERED FOR I OR Q DATA. 1, 2, 3, 4: RISING EDGE TRIGGERED. DELAY1 DELAY1 RETIMER-CLK DCLKIO-INT 4 IE IE OE DCLKIO (INPUT/OUTPUT) 07265-052 DELAY2 CLKIN (INPUT) NOTES: 1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE AD9716, AND 13 FOR THE AD9717. Figure 94.
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AD9714/AD9715/AD9716/AD9717 Table 15. Timer Register List Bit Name CLKMODEQ[1:0] Searching Reacquire CLKMODEN CLKMODEI[1:0] Description Q data path retimer clock selected output. Valid after the searching bit goes low. High indicates that the internal data path retimer is searching for the clock relationship (DAC is not usable until it is low again). Changing this bit from 0 to 1 causes the data path retimer circuit to reacquire the clock relationship.
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AD9714/AD9715/AD9716/AD9717 REFERENCE OPERATION REFERENCE CONTROL AMPLIFIER The AD9714/AD9715/AD9716/AD9717 contain an internal 1.0 V band gap reference. The internal reference can be disabled by setting Bit 0 (EXTREF) of the power-down register (Address 0x01) through the SPI interface. To use the internal reference, decouple the REFIO pin to AVSS with a 0.1 μF capacitor, enable the internal reference, and clear Bit 0 of the power-down register (Address 0x01) through the SPI interface.
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AD9714/AD9715/AD9716/AD9717 DAC TRANSFER FUNCTION The AD9714/AD9715/AD9716/AD9717 provide two differential current outputs, IOUTP/IOUTN and QOUTP/QOUTN. IOUTP and QOUTP provide a near full-scale current output, IxOUTFS, when all bits are high (that is, DAC CODE = 2N − 1, where N = 8, 10, 12, or 14 for the AD9714, AD9715, AD9716, and AD9717, respectively), while IOUTN and QOUTN, the complementary outputs, provide no current.
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AD9714/AD9715/AD9716/AD9717 SELF-CALIBRATION The AD9714/AD9715/AD9716/AD9717 have a self-calibration feature that improves the DNL of the device. Performing a selfcalibration on the device improves device performance in low frequency applications. The device performance in applications where the analog output frequencies are above 5 MHz are generally influenced more by dynamic device behavior than by DNL and, in these cases, self-calibration is unlikely to provide much benefit.
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AD9714/AD9715/AD9716/AD9717 COARSE GAIN ADJUSTMENT Option 3 Option 1 Even when the device is in pin mode, full-scale values can be adjusted by sourcing or sinking current from the FSADJx pins. Any noise injected here appears as amplitude modulation of the output. Thus, a portion of the required series resistance (at least 20 kΩ) must be installed right at the pin. A range of ±10% is quite practical using this method.
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AD9714/AD9715/AD9716/AD9717 1200 USING THE INTERNAL TERMINATION RESISTORS CML RCML RLIN 500Ω IOUTN I DAC OR Q DAC RLIP 07265-057 IOUTP 500Ω Figure 101. Simplified Internal Load Options 1100 1000 900 RESISTANCE (Ω) 800 700 600 500 400 300 200 0 8 16 24 32 CODE 40 48 56 07265-058 The AD9717/AD9716/AD9715/AD9714 have four 500 Ω termination internal resistors (two for each DAC output).
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AD9714/AD9715/AD9716/AD9717 APPLICATIONS INFORMATION OUTPUT CONFIGURATIONS The following sections illustrate some typical output configurations for the AD9714/AD9715/AD9716/AD9717. Unless otherwise noted, it is assumed that IxOUTFS is set to a nominal 2 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration can consist of either an RF transformer or a differential op amp configuration.
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AD9714/AD9715/AD9716/AD9717 DIFFERENTIAL BUFFERED OUTPUT USING AN OP AMP A dual op amp (see the circuit shown in Figure 105) can be used in a differential version of the single-ended buffer shown in Figure 104. The same RC network is used to form a one-pole differential, low-pass filter to isolate the op amp inputs from the high frequency images produced by the DAC outputs.
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AD9714/AD9715/AD9716/AD9717 AD9714/AD9715/ AD9716/AD9717 I OR Q DAC 500Ω AD9714/AD9715/ AD9716/AD9717 AUX DAC The auxiliary DACs can be used for local oscillator (LO) cancellation when the DAC output is followed by a quadrature modulator. This LO feedthrough is caused by the input referred dc offset voltage of the quadrature modulator (and the DAC output offset voltage mismatch) and can degrade system performance.
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To achieve LO feedthrough compensation, the user should start with the default conditions of the AUXDAC registers, and then increment the magnitude of one or the other AUXDAC output voltages. While this is being done, the amplitude of the LO feedthrough at the quadrature modulator output should be sensed. If the LO feedthrough amplitude increases, try either decreasing the output voltage of the AUXDAC being adjusted, or try adjusting the output voltage of the other AUXDAC.
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AD9714/AD9715/AD9716/AD9717 MODIFYING THE EVALUATION BOARD TO USE THE ADL5370 ON-BOARD QUADRATURE MODULATOR To evaluate the ADL5370 on this board, the population of these same components should be reversed so that they are in the following positions: The evaluation board contains an Analog Devices, Inc., ADL5370 quadrature modulator. The AD9714/AD9715/ AD9716/AD9717 and the ADL5370 provide an easy-tointerface DAC/modulator combination that can be easily characterized on the evaluation board.
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5V J3 5V 2 1 SMAEDGE 1 2 3 4 U2 U4 U6 U7 5V RC0603 78.7K 5VIN R3 NC FB OUT6 SD OUT5 IN4 R29 8 7 6 5 OUT5 5 OUT6 6 FB 7 NC 8 R10 FB 7 NC 8 IN3 5V RC0603 78.7K GND ADP3334 SD IN4 5V 78.7K RC0603 R5 NC FB OUT5 5 OUT6 6 RC0603 GND ADP3334 SD IN4 5V 78.
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6 5 34 36 38 40 33 35 37 39 1IN DB10X DB11X DB7X DB8X DB1X DB0X DB0X DB2X DB1X DB4X DB3X DB3X DB5X DB4X DB2X DB6X DB5X DB6X DB7X DB8X DB9X DB9X DB11X DB12X DB10X DB12X DB13X DB13X DIGITAL INPUTS J1 AND RP3, THE MSB IS DB13, DB11, DB9, OR DB7, DEPENDING ON THE PART.
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Figure 114. Clock Input and DUT Rev. A | Page 55 of 80 RC0402 C 2 1 C24 CC0603 0.1UF C26 CC0603 0.1UF AVDD C27 CC0603 0.1UF C C77 00.1UF CVDD R107 DNP R108 10K U12 OUT C 23 CC0603 0.01UF DVDD C25 CC0603 0.01UF C 28 CC0603 0.01UF OSC-S1703 GND OVCC 4 TP30 WHT C39 CC0603 1UF 00.
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FSADJ1 32K 0.1% R1 TP1 WHT IOT_CML RC0805 RC0805 8K 0.1% R51 R22 DNP R99 100K TP34 WHT JP90 R97 DNP S9 REFIO IOUT NETWORK AND FSADJ1 RC0603 100K OPAMPIN R35 RC0402 R117 0 R94 T2 C107 3 2 RC0603 6 4 CC0603 0.1UF RC0402 RC0402 0 S ADTL1-12 P R115 499 R116 0 WHT TP44 1 3 R93 RC0603 0 RC0603 1 N5V 4 C108 5 DNP AGND;9 0.1UF 0.
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FSADJ2 QOT_CML QOUTB TP17 WHT CC0603 RC0603 32K 0.1% R58 C48 0.1UF R52 DNP R54 DNP JP82 RC0603 8K 0.1% R60 RC0805 RC0805 RC0805 R102 100K TP35 WHT DNP R101 DNP TP37 DNP C96 CC0603 RC0603 FSADJ resistors must have low TC 16K 0.1% R59 JP91 WHEN R52 AND R53 ARE NOT DNP, 499 IS RECOMMENDED R53 DNP JP20 QOUTA RC0603 JP21 ERA6YEB323V, ERA6Y RC0603 JP16 ERA6YEB323V, ERA6Y Rev. A | Page 57 of 80 ERA6YEB323V, ERA6Y Figure 116.
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MLX-0532610571 Figure 117. SPI Port Rev. A | Page 58 of 80 0 0 R82 5V RC0402 R62 RC0402 SLEEP-CSB RMODE-SCLK MODE-SDIO MODE-SDO P3 pcb bottom side MP2 5 4 3 2 1 MP1 R39 R40 22 22 22RC0402 R41 R28 22 DVDDX C114 CC0603 0.1UF 5VUSB 0.1UF 8 10 9 11 12 13 14 C109 CC0603 0.
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L14 Rev. A | Page 59 of 80 Figure 118. Modulated Output L18 7.5PF DNP C93 CC0805 DNP C94 3 1 RC0603 R78 4 6 RC0603 R75 RC0603 ADTL1-12 0 4 R74 P NC=2,5 S T3 0 0 ADTL1-12 P NC=2,5 S 6 10UF 10V 100PF C50 CC0402 J6 ETC1-1-13 VDDM_IN 2 1 SMAEDGE AGND;3,4,5 CC0402 0.1UF C47 CC0402 CC0402 RED TP16 BLK TP21 4 MODULATED OUTPUT MOD_QP ACASE VDDM C43 MOD_QN MOD_IN MOD_IP P 4.7PF LC1008 LC1008 DNP R73 RC0603 T4 C64 CC0805 1.
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J10 C RC0805 CGND;3,4,5 C C C CVDDX R91 49.9 4 S 6 5 1 R77 CGND;5 3 4 RC0402 SW2 1.8K JTX-4-10T+ 1:4 2 3 1 P 2 T9 1.8K HSMS-281C C62 C CC0402 D3 RA0 1NF RC0402 R76 1 3 2 C46 C45 0 0.1UF RC0402 R86 0.1UF CC0402 CC0402 C CLOCK DRIVER CHIP CVDDX CVDDX CVDDX SLEEP-CSB MODE-SDO MODE-SDIO RMODE-SCLK CVDDX CVDDX CVDDX CVDDX 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 GND3 VS13 FUNC STATUS VS7 GND2 Figure 119.
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AD9714/AD9715/AD9716/AD9717 07265-203 SILKSCREENS Figure 120. Layer 2, Ground Plane Rev.
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07265-204 AD9714/AD9715/AD9716/AD9717 Figure 121. Layer 3, Power Plane Rev.
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07265-205 AD9714/AD9715/AD9716/AD9717 Figure 122. Assembly—Primary Side Rev.
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07265-206 AD9714/AD9715/AD9716/AD9717 Figure 123. Assembly—Secondary Side Rev.
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07265-217 AD9714/AD9715/AD9716/AD9717 Figure 124. Solder Mask—Primary Side with Socket Rev.
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07265-207 AD9714/AD9715/AD9716/AD9717 Figure 125. Solder Mask—Secondary Side Rev.
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07265-208 AD9714/AD9715/AD9716/AD9717 Figure 126. Hard Gold Plated with Bumps and Socket Rev.
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07265-209 AD9714/AD9715/AD9716/AD9717 Figure 127. Primary Side Paste Rev.
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07265-210 AD9714/AD9715/AD9716/AD9717 Figure 128. Secondary Side Paste Rev.
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07265-211 AD9714/AD9715/AD9716/AD9717 Figure 129. Silkscreen—Primary Side Rev.
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07265-212 AD9714/AD9715/AD9716/AD9717 Figure 130. Silkscreen—Secondary Side Rev.
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07265-213 AD9714/AD9715/AD9716/AD9717 Figure 131. Layer 1—Primary Side Rev.
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07265-214 AD9714/AD9715/AD9716/AD9717 Figure 132. Layer 4—Secondary Side Rev.
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07265-215 AD9714/AD9715/AD9716/AD9717 Figure 133. Immersion Gold, No Socket, No Bumps Rev.
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07265-216 AD9714/AD9715/AD9716/AD9717 Figure 134. Solder Mask—Primary Side, No Socket Rev.
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AD9714/AD9715/AD9716/AD9717 BILL OF MATERIALS Table 18.
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AD9714/AD9715/AD9716/AD9717 Qty 11 Device IND1812 Package LC1812 Description EXC-CL4532U1 4 4 1 1 1 Reference Designator L1, L2, L3, L4, L5, L6, L7, L12, L13, L16, L19 L8, L9, L10, L11 L14, L17, L18, L20 L15 P1 P3 IND1008 IND1008 IND1210 USB-MINIB Molex 0532610571 LC1008 LC1008 LC1210 USB-MINIB Molex 0532610571 2 R1, R58 RC0805 RC0805 1.8 μH, 10% DNP EXC-CL3225U1 USB mini 5-pin 1.25 mm, 5-pin wireto-board connector 32 kΩ, 0.
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AD9714/AD9715/AD9716/AD9717 Qty 2 2 4 1 Reference Designator RP3, RP4 SW1, SW2 T1, T2, T3, T6 T4 Device RNETCTS743-8 KEYBDSWG ADTL1-12 ETC1-1-13 Package RNETCTS743-8 OMRONB3SG MINI_CD542 SM-22 Description 22 Ω resistor B3S-1100 push-button DNP M/A COM ETC1-1-13 2 T5, T8 ADT9-1T MINI_CD542 ADT9-1T 1 T9 JTX-4-10T MINI_BH292 JTX-4-10T+ 16 LOOPMINI LOOPMINI White test point LOOPMINI LOOPMINI LOOPMINI LOOPMINI DNP Red test point LOOPMINI LOOPMINI LOOPMINI LOOPMINI DNP Black test point 1
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AD9714/AD9715/AD9716/AD9717 OUTLINE DIMENSIONS 6.00 BSC SQ 0.60 MAX 0.60 MAX TOP VIEW 0.50 BSC 5.75 BSC SQ 0.50 0.40 0.30 12° MAX 0.80 MAX 0.65 TYP 0.30 0.23 0.18 1 4.25 4.10 SQ 3.95 EXPOSED PAD (BOT TOM VIEW) 21 20 11 10 0.25 MIN 4.50 REF 0.05 MAX 0.02 NOM SEATING PLANE 40 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.