0-/12-/14-Bit, 1200 MSPS DACS AD9734/AD9735/AD9736 FEATURES FUNCTIONAL BLOCK DIAGRAM RESET A reduced-specification LVDS interface is utilized to achieve the high sample rate. The output current can be programmed over a range of 8.66 mA to 31.66 mA. The AD973x family is manufactured on a 0.18 μm CMOS process and operates from 1.8 V and 3.3 V supplies for a total power consumption of 380 mW in bypass mode. It is supplied in a 160-lead chip scale ball grid array for reduced package parasitics.
AD9734/AD9735/AD9736 TABLE OF CONTENTS Features .............................................................................................. 1 Full Scale Current (FSC) Registers (Reg. 2, Reg. 3)............... 31 Applications....................................................................................... 1 LVDS Controller (LVDS_CNT) Registers (Reg. 4, Reg. 5, Reg. 6) ............................................................... 31 General Description ..........................................
AD9734/AD9735/AD9736 Operating the LVDS Controller in Surveillance and Auto Mode ...................................................................................41 SYNC Logic and Controller...........................................................42 SYNC Logic and Controller Operation....................................42 Operation in Manual Mode.......................................................42 Operation in Surveillance and Auto Modes ............................42 FIFO Bypass...................
AD9734/AD9735/AD9736 SPECIFICATIONS DC SPECIFICATIONS AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, maximum sample rate, IFS = 20 mA, 1× mode, 25 Ω, 1% balanced load, unless otherwise noted. Table 1.
AD9734/AD9735/AD9736 Parameter Static, No Clock IAVDD33 ICVDD18 IDVDD33 IDVDD18 FIR Bypass (1×) Mode Sleep Mode, No Clock IAVDD33 FIR Bypass (1×) Mode Power-Down Mode 3 IAVDD33 ICVDD18 IDVDD33 IDVDD18 FIR Bypass (1×) Mode Min AD9736 Typ Max 25 8 10 2 133 Min AD9735 Typ Max 25 8 10 2 133 Min AD9734 Typ Max 25 8 10 2 133 Unit mA mA mA mA mW 2.5 59 3.15 65 2.5 59 3.15 65 2.5 59 3.15 65 mA mW 0.01 0.02 0.01 0.01 0.12 0.13 0.12 0.12 0.11 1.24 0.01 0.02 0.01 0.01 0.12 0.13 0.12 0.12 0.
AD9734/AD9735/AD9736 DIGITAL SPECIFICATIONS AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, maximum sample rate, IFS = 20 mA, 1× mode, 25 Ω, 1% balanced load, unless otherwise noted. LVDS drivers and receivers are compliant to the IEEE-1596 reduced range link, unless otherwise noted. Table 2.
AD9734/AD9735/AD9736 Parameter INPUT (SDI, SDIO, SCLK, CSB) Voltage in High, VIH Voltage in Low, VIL Current in High, IIH Current in Low, IIL SDIO OUTPUT Voltage out High, VOH Voltage out Low, VOL Current out High, IOH Current out Low, IOL Min Max Unit −10 −10 0.8 +10 +10 V V μA μA 2.4 0 3.6 0.4 2.0 Typ 3.3 0 4 4 1 Refer to the Input Data Timing section for recommended LVDS differential drive levels. Rev.
AD9734/AD9735/AD9736 AC SPECIFICATIONS AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, maximum sample rate, IFS = 20 mA, 1× mode, 25 Ω, 1% balanced load, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE Maximum Update Rate SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 800 MSPS fOUT = 20 MHz fDAC = 1200 MSPS fOUT = 50 MHz fOUT = 100 MHz fOUT = 316 MHz fOUT = 550 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 1200 MSPS fOUT2 = fOUT + 1.
AD9734/AD9735/AD9736 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter AVDD33 DVDD33 DVDD18 CVDD18 AVSS AVSS DVSS CLK+, CLK− PIN_MODE DATACLK_IN, DATACLK_OUT LVDS Data Inputs IOUTA, IOUTB I120, VREF, IPTAT IRQ, CSB, SCLK, SDO, SDIO, RESET Junction Temperature Storage Temperature With Respect to AVSS DVSS DVSS CVSS DVSS CVSS CVSS CVSS DVSS DVSS Min −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V −0.3 V Max +3.6 V +3.6 V +1.98 V +1.98 V +0.3 V +0.3 V +0.3 V CVDD18 + 0.18 V DVDD33 + 0.
AD9734/AD9735/AD9736 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D DACCLK– E DACCLK+ F G H J K DB13 (MSB) L DB12 DB0 (LSB) M DB11 N 04862-005 DB9 DB10 DB8 DB7 DB6 DATACLK_IN DB5 DATACLK_OUT DB4 DB3 DB2 DB1 P Figure 2. AD9736 Digital LVDS Input, Clock I/O (Top View) Table 6. AD9736 Pin Function Descriptions Pin No.
AD9734/AD9735/AD9736 Pin No. K1, K2, K3, K4, K11, K12, L2, L3, L4, L5, L6, L9, L10, L11, L12, M3, M4, M5, M6, M9, M10, M11, M12 K13, K14 Mnemonic DVSS Description Digital Supply Ground.
AD9734/AD9735/AD9736 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D DACCLK– E DACCLK+ F G H J K DB11 (MSB) L DB10 DB9 NC M N 04862-115 DB8 DB7 DB6 DB5 DB4 DATACLK_IN DB3 DATACLK_OUT DB2 DB1 NC DB0 (LSB) P Figure 3. AD9735 Digital LVDS Input, Clock I/O (Top View) Table 7. AD9735 Pin Function Descriptions Pin No.
AD9734/AD9735/AD9736 Pin No.
AD9734/AD9735/AD9736 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D DACCLK– E DACCLK+ F G H J K DB9 (MSB) L DB8 NC M DB7 N 04862-114 DB6 DB5 DB4 DB3 DB2 DATACLK_IN DB1 DATACLK_OUT NC DB0 (LSB) NC NC P Figure 4. AD9734 Digital LVDS Input, Clock I/O (Top View) Table 8. AD9734 Pin Function Descriptions Pin No.
AD9734/AD9735/AD9736 Pin No. K13, K14 Mnemonic DB<9>−/DB<9>+ L1 PIN_MODE L7, L8, M7, M8, N7, N8, P7, P8 L13, L14 DVDD33 DB<8>−/DB<8>+ M1, M2 M13, M14 NC DB<7>−/DB<7>+ N1, P1 N2, P2 N3, P3 N4, P4 NC NC NC DB<0>−/DB<0>+ N5, P5 DB<1>−/DB<1>+ N6, P6 N10, P10 DATACLK_OUT−/ DATACLK_OUT+ DATACLK_IN−/ DATACLK_IN+ DB<2>−/DB<2>+ N11, P11 DB<3>−/DB<3>+ N12, P12 DB<4>−/DB<4>+ N13, P13 DB<5>−/DB<5>+ N14, P14 DB<6>−/DB<6>+ N9, P9 Description Negative/Positive Data Input Bit 9 (MSB).
AD9734/AD9735/AD9736 LOCATION OF SUPPLY AND CONTROL PINS 5 6 7 8 9 10 11 12 13 14 1 A A B B C C D D E E F F G G H H J J K K L L M M N N P P AVDD33, 3.3V, ANALOG SUPPLY AVSS, ANALOG SUPPLY GROUND SHIELD 2 3 4 5 6 7 8 4 5 6 7 8 9 10 11 12 13 14 DVDD33, 3.3V DIGITAL SUPPLY DVSS DIGITAL SUPPLY GROUND Figure 7. Digital Supply Pins (Top View) Figure 5. Analog Supply Pins (Top View) 1 3 DVDD18, 1.
AD9734/AD9735/AD9736 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) The maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages.
AD9734/AD9735/AD9736 TYPICAL PERFORMANCE CHARACTERISTICS AD9736 STATIC LINEARITY, 10 mA FULL SCALE 1.00 1.0 0.75 0.8 0.50 0.6 0.25 0.4 ERROR (LSB) ERROR (LSB) 0 –0.25 –0.50 –0.75 –1.00 0.2 0 –0.2 –0.4 –1.25 –0.6 –1.50 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE –1.0 04862-008 –2.00 0 Figure 9. AD9736 INL, −40°C, 10 mA FS 2048 4096 6144 8192 10240 12288 14336 16384 CODE 04862-010 –0.8 –1.75 Figure 12. AD9736 DNL, −40°C, 10 mA FS 1.00 1.0 0.75 0.8 0.50 0.6 0.25 0.
AD9734/AD9735/AD9736 0.6 0.8 0.5 0.6 0.4 0.4 0.3 0.2 0.2 0 –0.2 –0.4 –0.6 0.1 0 –0.1 –0.2 –0.8 –0.3 –1.0 –0.4 –1.2 –0.5 2048 4096 6144 8192 10240 12288 14336 16384 CODE –0.6 0 0.6 0.8 0.5 0.6 0.4 0.4 0.3 0.2 0.2 ERROR (LSB) 1.0 0 –0.2 –0.4 –0.6 0 –0.2 –0.3 –0.4 –1.2 –0.5 2048 4096 6144 8192 10240 12288 14336 16384 CODE –0.6 0 0.6 0.8 0.5 0.6 0.4 0.4 0.3 0.2 0.2 ERROR (LSB) 1.0 0 –0.2 –0.4 –0.6 –0.2 –0.4 –1.2 –0.
AD9734/AD9735/AD9736 AD9736 STATIC LINEARITY, 30 mA FULL SCALE 2.0 0.6 0.5 1.5 0.4 0.3 0.2 0.5 ERROR (LSB) 0 –0.5 –1.0 0 –0.1 –0.2 –0.3 –0.4 –1.5 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE –0.6 0 Figure 21. AD9736 INL, −40°C, 30 mA FS 6144 8192 10240 12288 14336 16384 CODE 0.6 0.5 1.5 0.4 1.0 0.3 0.2 0.5 ERROR (LSB) ERROR (LSB) 4096 Figure 24. AD9736 DNL, −40°C, 30 mA FS 2.0 0 –0.5 –1.0 0.1 0 –0.1 –0.2 –0.3 –0.4 –1.5 –0.
AD9734/AD9735/AD9736 AD9735 STATIC LINEARITY, 10 mA, 20 mA, 30 mA FULL SCALE 0.4 0.100 0.050 0.3 0 ERROR (LSB) ERROR (LSB) 0.2 0.1 –0.050 –0.100 0 –0.150 –0.1 512 1024 1536 2048 2560 3072 3584 4096 CODE –0.250 0 512 1024 1536 2048 2560 3072 3584 4096 3584 4096 3584 4096 CODE Figure 27. AD9735 INL, 25°C, 10 mA FS 04862-028 0 04862-025 –0.2 –0.200 Figure 30. AD9735 DNL, 25°C, 10 mA FS 0.15 0.100 0.075 0.10 0.050 0.05 ERROR (LSB) ERROR (LSB) 0.025 0 –0.05 0 –0.
AD9734/AD9735/AD9736 AD9734 STATIC LINEARITY, 10 mA, 20 mA, 30 mA FULL SCALE 0.04 0.03 0.02 0.02 ERROR (LSB) 0.04 0 0.01 0 –0.04 –0.01 –0.06 0 128 256 384 512 640 768 896 1024 CODE 04862-031 –0.02 –0.02 0 128 256 384 512 640 768 896 1024 CODE 04862-034 ERROR (LSB) 0.06 Figure 36. AD9734 DNL, 25°C, 10 mA FS Figure 33. AD9734 INL, 25°C, 10 mA FS 0.03 0.03 0.02 0.02 0.01 0.01 ERROR (LSB) –0.01 –0.02 0 –0.01 –0.03 –0.04 –0.
AD9734/AD9735/AD9736 AD9736 POWER CONSUMPTION, 20 mA FULL SCALE 0.50 0.7 0.45 0.6 TOTAL 0.40 TOTAL 0.5 0.25 0.20 DVDD18 0.15 DVDD18 0.3 CVDD18 0.2 AVDD33 0.10 DVDD33 0 250 500 750 fDAC (MHz) 1000 1250 1500 0 DVDD33 AVDD33 0.1 CVDD18 0.05 0 0.4 0 250 500 750 1000 1250 1500 fDAC (MHz) Figure 40. AD9736, 2× Interpolation Mode Power vs. fDAC at 25°C Figure 39. AD9736 1× Mode Power vs. fDAC at 25°C Rev. A | Page 23 of 72 04862-038 POWER (W) 0.30 04862-037 POWER (W) 0.
AD9734/AD9735/AD9736 80 75 800MSPS IMD (dBc) SFDR (dBc) 70 65 60 1.2GSPS 1GSPS 50 0 50 100 150 200 250 300 350 400 450 500 550 600 fOUT (MHz) 04862-039 55 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 0 50 100 150 200 Figure 41. AD9736 SFDR vs. fOUT over fDAC at 25°C 300 350 400 450 500 550 Figure 44. AD9736 IMD vs. fOUT over 50 Parts, 25°C,1.
AD9734/AD9735/AD9736 95 90 90 85 IMD 0dBFS 80 75 IMD (dBc) SFDR 75 70 –6dBFS 65 65 60 60 55 0 10 fOUT (MHz) 100 50 0 300 400 500 600 Figure 50. AD9736 IMD vs. fOUT over AOUT, 25°C, 1.2 GSPS 90 90 THIRD-ORDER IMD 85 85 SFDR 80 SFDR, IMD (dBc) 75 70 65 75 70 SFDR_1× 65 60 60 55 55 0 50 100 150 200 fOUT (MHz) SFDR_2× 80 250 300 350 50 04862-046 SFDR, IMID (dBc) 200 fOUT (MHz) Figure 47. AD9736 Low Frequency IMD and SFDR vs. fOUT, 25°C, 1.
AD9734/AD9735/AD9736 –150 –150 –152 –152 –154 –154 –156 1.2GSPS –160 –162 –160 –164 –166 –166 –168 –168 0 100 200 300 fOUT (MHz) 400 500 600 –170 –40°C +25°C 0 100 200 300 400 500 600 fOUT (MHz) Figure 56. AD9736 8-Tone NSD vs. fOUT over Temperature, 1.2 GSPS Figure 53. AD9736 1-Tone NSD vs.
AD9734/AD9735/AD9736 AD9735, AD9734 DYNAMIC PERFORMANCE, 20 mA FULL SCALE 80 90 85 75 1GSPS 80 800MSPS 75 IMD (dBc) SFDR (dBc) 70 65 60 800MSPS 70 1.2GSPS 65 1GSPS 60 0 50 100 150 200 250 300 350 400 450 500 550 600 fOUT (MHz) 50 04862-060 50 55 1.2GSPS 0 Figure 59. AD9735 SFDR vs. fOUT over fDAC, 1.2 GSPS 50 100 150 200 250 300 350 400 450 500 550 600 fOUT (MHz) 04862-063 55 Figure 62. AD9734 IMD vs. fOUT over fDAC, 1.
AD9734/AD9735/AD9736 AD973x WCDMA ACLR, 20 mA FULL SCALE REF –22.75dBm #AVG LOG 10dB/ 04862-057 #ATTEN 6dB PAVG 10 W1 S2 CENTER 134.83MHz #RES BW 30kHz RMS RESULTS CARRIER POWER –10.72dBm/ 3.84000MHz VBW 300kHz OFFSET FREQ 5.00MHz 10.0MHz 15.0MHz REF BW 3.840MHz 3.840MHz 3.884MHz LOWER dBc dBm –81.65 –92.37 –82.06 –92.78 –82.11 –92.83 SPAN 33.88MHz SWEEP 109.9ms (601pts) UPPER dBc –81.39 –82.43 –82.39 dBm –92.11 –93.16 –93.11 Figure 65. AD9736 WCDMA Carrier at 134.83 MHz, fDAC = 491.
AD9734/AD9735/AD9736 SPI REGISTER MAP Write 0 to unspecified or reserved bit locations. Reading these bits returns unknown values. Table 9. SPI Register Map Reg. Addr. Dec. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Hex.
AD9734/AD9735/AD9736 SPI REGISTER DETAILS Reading these registers returns previously written values for all defined register bits, unless otherwise noted. Reset value for write registers in bold text. MODE REGISTER (REG. 0) ADDR 0x00 Name MODE Bit 7 SDIO_DIR Bit 6 LSB/MSB Bit 5 RESET Bit 4 LONG_INS Bit 3 2× MODE Bit 2 FIFO MODE Bit 1 DATAFRMT Bit 0 PD Table 10.
AD9734/AD9735/AD9736 FULL SCALE CURRENT (FSC) REGISTERS (REG. 2, REG. 3) ADDR 0x02 0x03 Name FSC_1 FSC_2 Bit 7 SLEEP FSC<7> Bit 6 – FSC<6> Bit 5 Bit 4 Bit 3 Bit 2 – FSC<5> – FSC<4> – FSC<3> – FSC<2> Bit 1 FSC<9> FSC<1> Bit 0 FSC<8> FSC<0> Bit 1 MHD<1> ERR_LO LTRH<1> Bit 0 MHD<0> CHECK LTRH<0> Table 12. Full Scale Current Output Register Bit Descriptions Bit Name SLEEP Read/Write WRITE FSC<9:0> WRITE Description 0, enable DAC output. 1, set DAC output current to 0 mA.
AD9734/AD9735/AD9736 SYNC CONTROLLER (SYNC_CNT) REGISTERS (REG. 7, REG. 8) ADDR 0x07 0x08 Name SYNC_CNT1 SYNC_CNT2 Bit 7 FIFOSTAT3 SSURV Bit 6 FIFOSTAT2 SAUTO Bit 5 FIFOSTAT1 SFLT<3> Bit 4 FIFOSTAT0 SFLT<2> Bit 3 VALID SFLT<1> Bit 2 SCHANGE SFLT<0> Bit 1 PHOF<1> RESERVED Bit 0 PHOF<0> STRH<0> Table 14.
AD9734/AD9735/AD9736 ANALOG CONTROL (ANA_CNT) REGISTERS (REG. 14, REG. 15) ADDR 0x0E 0x0F Name ANA_CNT1 ANA_CNT2 Bit 7 MSEL<1> HDRM<7> Bit 6 MSEL<0> HDRM<6> Bit 5 – HDRM<5> Bit 4 – HDRM<4> Bit 3 – HDRM<3> Bit 2 TRMBG<2> HDRM<2> Bit 1 TRMBG<1> HDRM<1> Bit 0 TRMBG<0> HDRM<0> Table 16. Analog Control Register Bit Descriptions Bit Name MSEL<1:0> Read/Write WRITE Description TRMBG<2:0> WRITE 000, band gap temperature characteristic trim. NOTE: See the plot in the Analog Control Registers section.
AD9734/AD9735/AD9736 CONTROLLER CLOCK PREDIVIDER (CCLK_DIV) READING REGISTER (REG. 22) ADR 0x16 Name CCLK_DIV Bit 7 RESERVED Bit 6 RESERVED Bit 5 RESERVED Bit 4 RESERVED Bit 3 CCD<3> Bit 2 CCD<2> Bit 1 CCD<1> Bit 0 CCD<0> Table 18. Controller Clock Predivider Register Bit Descriptions Bit Name CCD<3:0> Read/Write WRITE Description 0x0, controller clock = DACCLK/16. 0x1, controller clock = DACCLK/32. 0x2, controller clock = DACCLK/64 … 0xF, controller clock = DACCLK/524288.
AD9734/AD9735/AD9736 THEORY OF OPERATION The AD9736, AD9735, and AD9734 are 14-bit, 12-bit, and 10-bit DACs that run at an update rate up to 1.2 GSPS. Input data can be accepted up to the full 1.2 GSPS rate, or a 2× interpolation filter can be enabled (2× mode) allowing full speed operation with a 600 MSPS input data rate. The DATA and DATACLK_IN inputs are parallel LVDS, meeting the IEEE reduced swing LVDS specifications with the exception of input hysteresis.
AD9734/AD9735/AD9736 SERIAL PERIPHERAL INTERFACE The AD973x serial port is a flexible, synchronous serial communications port, allowing easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI® and Intel® SSR protocols. The interface allows read/write access to all registers that configure the AD973x.
AD9734/AD9735/AD9736 CSB—Chip Select Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. The SDO and SDIO pins go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle. SDIO—Serial Data I/O Data is always written into the AD973x on this pin. However, this pin can be used as a bidirectional data line.
AD9734/AD9735/AD9736 tDS Table 22. PIN_MODE Input Functions tSCLK Mnemonic UNSIGNED CSB tPWH tPWL SCLK 2× tDH INSTRUCTION BIT 7 SDIO 04862-071 tDS INSTRUCTION BIT 6 FSC1, FSC0 Figure 73. Timing Diagram for SPI Register Write CSB PD SCLK SDIO I1 I0 D7 FIFO tDV D6 D5 04862-072 tDNV Figure 74. Timing Diagram for SPI Register Read After the last instruction bit is written to the SDIO pin, the driving signal must be set to a high impedance in time for the bus to turn around.
AD9734/AD9735/AD9736 0.10 INTERPOLATION FILTER 0.08 0.06 0.04 MAGNITUDE (dB) In 2× mode, the input data is interpolated by a factor of 2 so that it aligns with the DAC update rate. The interpolation filter is a hard-coded, 55-tap, symmetric FIR with a 0.001 dB passband flatness and a stop-band attenuation of about 90 dB. The transition band runs from 20% of fDAC to 30% of fDAC. The FIR response is shown in Figure 75 where the frequency axis is normalized to fDAC.
AD9734/AD9735/AD9736 DBU The LVDS and sync controllers are independently operated in three modes via SPI port Reg. 6 and Reg. 8: Manual mode • Surveillance mode • Auto mode FF D1 FF D2 DBL DATA SAMPLING SIGNAL SD<3:0> SAMPLE DELAY In manual mode, all of the timing measurements and updates are externally controlled via the SPI. DATACLK_IN LVDS RX MSD<3:0> DELAY In surveillance mode, each controller takes measurements and calculates a new optimal value continuously.
AD9734/AD9735/AD9736 To find the leading edge of the data cycle, increment the measured setup delay until the check bit goes low. To find the trailing edge, increment the measured hold delay (MHD) until check goes low. Always set MHD = 0 when incrementing MSD and vice versa. SETUP TIME (tS) DB<13:0> DATACLK_IN SAMPLE DELAY SD<3:0> MSD<3:0> = 0 1 2 3 4 5 The incremental units of SD, MSD, and MHD are in units of real time, not fractions of a clock cycle. The nominal step size is 80 ps.
AD9734/AD9735/AD9736 SYNC LOGIC AND CONTROLLER A FIFO structure is utilized to synchronize the data transfer between the DACCLK and the DATACLK_IN clock domains. The sync controller writes data from DB<13:0> into an 8-word memory register based on a cyclic write counter clocked by the DSS, which is a delayed version of DACCLK_IN. The data is read out of the memory based on a second cyclic read counter clocked by DACCLK.
AD9734/AD9735/AD9736 DACCLK INTERNAL DELAY DATACLK_OUT EXTERNAL DELAY DATACLK_IN DATA_IN A C B D E F G I H J K L M N P O Q R SAMPLE_HOLD SAMPLE_SETUP SAMPLE_DELAY DSS1 C A D1 G E I Q O M K DSS2 0 2 1 3 H F 4 5 6 7 2 3 B DATA 'A' CAN BE SAFELY READ FROM THE FIFO IN THE SAFE ZONE. IN THE ERROR ZONE, THE POINTERS MAY BRIEFLY OVERLAP DUE TO CLOCK JITTER OR NOISE. 0 FIFOSTAT IS SET EQUAL TO THE WRITE POINTER EACH TIME THE READ POINTER CHANGES FROM 7 TO 0.
AD9734/AD9735/AD9736 DIGITAL BUILT-IN SELF TEST (BIST) OVERVIEW Placing the idle value on the data input also allows the BIST to be set up while the DAC clock is running. The idle value should be all 0s in unsigned mode (0x0000) and all 0s except for the MSB in twos complement mode (0x2000). The AD973x includes an internal signature generator that processes incoming data to create unique signatures.
AD9734/AD9735/AD9736 AD973x BIST PROCEDURE 17. Read all signature registers (Reg. 21, Reg. 20, Reg. 19, and Reg. 18, as described in Step 14 ) for each of the four SEL (Reg. 17, Bits 7:6) values, and verify that they match the expected signatures shown in Table 25. 18. Flush the BIST circuitry. This must be done once before valid data can be read. Loop back to Step 11 and rerun the test to obtain the correct result. 1. Set RESET pin = 1. 2. Set input DATA = 0x0000 for signed (0x2000 for unsigned).
AD9734/AD9735/AD9736 GENERATING EXPECTED SIGNATURES To generate the expected BIST signatures, follow this procedure: The following MATLAB code duplicates the internal logic of the AD973x. To use it, save this code in a file called bist.m. 1. --- begin bist.
AD9734/AD9735/AD9736 CROSS CONTROLLER REGISTERS Figure 85 shows the effect of UPDEL and DNDEL. If the system is calibrated after manufacture, adjust the cross controller offsets to provide optimum performance. To start, increment DNDEL<5:0> (Reg. 11, Bits 5:0) while observing HD2 (second harmonic distortion) and/or IMD to find the desired optimum. If DNDEL does not influence the performance, set it to 0 and increment UPDEL<5:0> (Reg. 10, Bits 5:0).
AD9734/AD9735/AD9736 ANALOG CONTROL REGISTERS –110 The AD973x includes some registers for optimizing its analog performance. These registers include temperature trim for the band gap, noise reduction in the output current mirror, and output current mirror headroom adjustments. NOISE (IdBm/Hz) –115 BAND GAP TEMPERATURE CHARACTERISTIC TRIM BITS Using TRMBG<2:0> (Reg.
AD9734/AD9735/AD9736 The full-scale output current range is approximately 10 mA to 30 mA for register values from 0x000 to 0x3FF. The default value of 0x200 generates 20 mA full scale. The typical range is shown in Figure 89. VREF (Pin C14) must be bypassed to ground with a 1 nF capacitor. The band gap voltage is present on this pin and can be buffered for use in external circuitry. The typical output impedance is near 5 kΩ.
AD9734/AD9735/AD9736 APPLICATIONS INFORMATION DRIVING THE DACCLK INPUT 0.1μF VCM = 400mV CLK– 04862-088 50Ω 0.1μF 50Ω CLK+ CLK– 50Ω BAV99ZXCT HIGH SPEED DUAL DIODE VCM = 400mV Figure 91. TTL or CMOS DACCLK Drive Circuit A simple bias network for generating VCM is shown in Figure 92. It is important to use CVDD18 and CVSS for the clock bias circuit. Any noise or other signal that is coupled onto the clock is multiplied by the DAC digital input signal and may degrade the DAC performance.
AD9734/AD9735/AD9736 DAC OUTPUT DISTORTION SOURCES This is the configuration implemented on the evaluation board (Figure 107). The 20 Ω series resistors allow the DAC to drive a less reactive load, which improves distortion. Further improvement is realized by adding the Balun T3 to help provide an equal load to both DAC outputs. The DAC architecture inherently generates third harmonics, the levels of which depend on the output frequency and amplitude generated.
AD9734/AD9735/AD9736 DC-COUPLED DAC OUTPUT An alternate circuit is shown in Figure 95. It suffers from dc offset at the output unless the DAC load resistors are small, relative to the amplifier gain and feedback resistors. 0.5V p-p 0V TO –0.5V IOUTA DAC OUTPUT 20mA FULL SCALE IOUTB 100Ω 25Ω 1kΩ 2kΩ AVSS 25Ω 1kΩ 2V p-p 0V TO –2V OUTPUT 2kΩ AVSS 2V p-p 0V TO –2V IOUTA Figure 95.
AD9734/AD9735/AD9736 DAC DATA SOURCES The circuit shown in Figure 96 allows optimum data alignment when running the AD973x at full speed. This circuit can be easily implemented in the FPGA or ASIC used to drive the digital input. It is important to use the DATACLK_OUT signal because it helps to cancel some of the timing errors. In this configuration, DATACLK_OUT generates the DDR LVDS DATACLK_IN to drive the AD973x.
AD9734/AD9735/AD9736 INPUT DATA TIMING The AD973x is intended to operate with the LVDS and sync controllers running to compensate for timing drift due to voltage and temperature variations. In this mode, the key to correct data capture is to present valid data for a minimum amount of time. The AD973x minimum valid data time is measured by increasing the input data rate to the point of failure. The nominal supply voltages are used and the temperature is set to the worst case of 85°C.
AD9734/AD9735/AD9736 SYNCHRONIZATION TIMING When more than one AD973x must be synchronized or when a constant group delay must be maintained, the internal controllers cannot be used. If the FIFO is enabled, the delay between multiple AD973x devices is unknown. If the DATACLK_OUT from multiple devices is used, there is an uncertainty of two DACCLK periods because the initial phase of DATACLK_OUT with respect to DACCLK cannot be controlled.
AD9734/AD9735/AD9736 POWER SUPPLY SEQUENCING The 1.8 V supplies should be enabled prior to enabling the 3.3 V supplies. Do not enable the 3.3 V supplies when the 1.8 V supplies are off.
AD9734/AD9735/AD9736 AD973X EVALUATION BOARD SCHEMATICS TP4 RED FERRITE VDD33 LC1210 + ACASE C14 10μF 6.3V VSS TB1 2 L7 TP7 RED FERRITE LC1210 18DIG TB1 3 VSS TP5 BLK L5 VDD18B + C22 ACASE 10μF 6.3V FERRITE LC1210 TP13 BLK TP6 RED + ACASE VSS TB1 4 VSS VDD18A L1, L3, L4, L5, L6, AND L7 FERRITE BEAD CORE: PANASONIC EXC–CL3225U1 DIGIKEY PN: P9811CT–ND C18 10μF 6.3V TP14 BLK VSS JP1 VSS L1 33ANA TB2 1 FERRITE LC1210 VSSA TB2 4 C1 10μF 6.
Rev. A | Page 58 of 72 Figure 105. Circuitry Local to AD973x, Evaluation Board, Rev. F ACASE 04862-103 VSSA 6.3V 4.7μF C11 VDDC C13 C12 1nF CC0603 0.
Rev. A | Page 59 of 72 Figure 106. High Speed Digital I/O Connector, AD973x Evaluation Board, Rev. F DB0 DB13 DB13 DB0 04862–104 AD9736 CONNECTOR NOTE: AD9736 MSB-LSB BIT ORDER IS REVERSED FROM THE CONNECTOR BIT ORDER.
Rev. A | Page 60 of 72 Figure 107. Clock Input and Analog Output, AD973x Evaluation Board, Rev. F 04862–105 VSSA IP IN R7 DNP RC0603 RC0603 VSSA RC0603 RC0603 RC0603 R19 20Ω R17 20Ω RC0603 R18 DNP RC0603 R17 AND R19 PRESENT A MORE REAL LOAD TO THE DAC WHICH IMPROVES H2 PERFORMANCE. R8 50Ω R6 50Ω RC0603 VSSA J1 VSSA;3,4,5 SMA200UP R162 0Ω R161 0Ω S T3 NC=2 S P P 5 4 3 2 1 P T3B T3:M/A-COM –1dB: 4.
Rev. A | Page 61 of 72 Figure 108. SPI Port Interface, AD973x Evaluation Board, Rev.
AD9734/AD9735/AD9736 04862-107 NOTE: THE AD9736 IS SOLDERED DIRECTLY TO THE PCB. THE SOCKET IS NOT INSTALLED. SILKSCREEN ERROR: SPI AND PIN ARE REVERSED. AD973X EVALUATION BOARD PCB LAYOUT Figure 109. CB Layout Top Placement, AD973x Evaluation Board, Rev. F Rev.
04860-108 AD9734/AD9735/AD9736 Figure 110. PCB Layout Layer 1, AD973x Evaluation Board, Rev. F Rev.
04861-109 AD9734/AD9735/AD9736 Figure 111. PCB Layout Layer 2, AD973x Evaluation Board, Rev. F Rev.
04862-110 AD9734/AD9735/AD9736 Figure 112. PCB Layout Layer 3, AD973x Evaluation Board, Rev. F Rev.
014862-111 AD9734/AD9735/AD9736 Figure 113. PCB Layout Layer 4, AD973x Evaluation Board, Rev. F Rev.
04862-112 AD9734/AD9735/AD9736 Figure 114. PCB Layout Bottom Placement, AD973x Evaluation Board, Rev. F Rev.
04862-113 4. WARP AND TWIST +/– .005 INCH PER INCH. 5. DIMENTIONS: ARE FOR THE FINISHED PART 6. SOLDER MASK: LIQUID PHOTO IMAGABLE SOLDER MASK COLOR GREEN, BOTH SIDES USING THE PATTERN(S) PROVIDED. NO MASK IS PERMITTED ON THE EXPOSED AREAS. SOLDER MASK TO ETCH REGISTRATION +/– .002 INCH TOTAL 7. SCREENING: SCREEN COMPONENT OUTLINES AND NOMENCLATURE USING OPAQUE WHITE INK ON THE PRIMARY AND SECONDARY SIDES (AS REQUIRED). NOMENCLATURE SHALL BE LEGIBLE. SCREEN TO ETCH REGISTRATION +/– .005 INCH TOTAL. 8.
AD9734/AD9735/AD9736 OUTLINE DIMENSIONS A1 CORNER INDEX AREA 12.10 12.00 SQ 11.90 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BALL A1 INDICATOR 10.40 BSC SQ TOP VIEW BOTTOM VIEW 0.80 REF DETAIL A A B C D E F G H J K L M N P 0.80 BSC 1.40 MAX DETAIL A 1.00 MAX 0.85 MIN 0.43 MAX 0.25 MIN 0.55 0.50 0.45 BALL DIAMETER SEATING PLANE 0.12 MAX COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-205-AE. Figure 116.
AD9734/AD9735/AD9736 NOTES Rev.
AD9734/AD9735/AD9736 NOTES Rev.
AD9734/AD9735/AD9736 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04862-0-9/06(A) Rev.
