Datasheet

AD9734/AD9735/AD9736
Rev. A | Page 50 of 72
APPLICATIONS INFORMATION
DRIVING THE DACCLK INPUT
The DACCLK input requires a low jitter differential drive
signal. It is a PMOS input differential pair powered from the
1.8 V supply, so it is important to maintain the specified 400 mV
input common-mode voltage. Each input pin can safely swing
from 200 mV p-p to 800 mV p-p about the 400 mV common-
mode voltage. While these input levels are not directly LVDS
compatible, DACCLK can be driven by an offset ac-coupled
LVDS signal, as shown in
Figure 90.
04862-088
LVDS_P_IN CLK+
50Ω
50Ω
0.1μF
0.1μF
LVDS_N_IN CLK–
V
CM
= 400mV
Figure 90. LVDS DACCLK Drive Circuit
If a clean sine clock is available, it can be transformer-coupled
to DACCLK, as shown in
Figure 107. Use of a CMOS or TTL
clock can also be acceptable for lower sample rates. It is routed
through a CMOS to LVDS translator, then ac-coupled, as
described previously. Alternatively, it can be transformer-
coupled and clamped, as shown in
Figure 91.
04862-089
50Ω
50Ω
TTL OR CMOS
CLK INPUT
CLK+
CLK–
V
CM
= 400mV
BAV99ZXCT
HIGH SPEED
DUAL DIODE
0.1μF
Figure 91. TTL or CMOS DACCLK Drive Circuit
A simple bias network for generating V
CM
is shown in
Figure 92. It is important to use CVDD18 and CVSS for the
clock bias circuit. Any noise or other signal that is coupled onto
the clock is multiplied by the DAC digital input signal and may
degrade the DAC performance.
0
4862-090
0.1µF 1nF
1nF
V
CM
= 400m
V
CVDD
1.8V
CVSS
1kΩ
2
87
Ω
Figure 92. DACCLK V
CM
Generator Circuit