Datasheet

AD9737A/AD9739A Data Sheet
Rev. | Page 52 of 64
The LVDS receivers include 100 Ω termination resistors, as shown
in Figure 163. These receivers meet the IEEE-1596.3-1996
reduced swing specification (with the exception of input hysteresis,
which cannot be guaranteed over all process corners). Figure 164
and Table 26 show an example of nominal LVDS voltage levels
seen at the input of the differential receiver with resulting
common-mode voltage and equivalent logic level. Note that
the AD9737A/AD9739A LVDS inputs do not include fail-safe
capability; hence, any unused input should be biased with an
external circuit or static driver. The LVDS receivers can be
powered-down via Register 0x01, Bit 4.
LVDS INPUTS
(NO FAIL-SAFE)
V
P
LVDS
RECEIVER
GND
100Ω
V
N
V
P,N
V
COM
= (V
P
+ V
N
)/2
LOGIC BIT
EQUIVALENT
V
P
V
N
V
P
V
N
Example
1.4V
1.0V
0.4V
–0.4V
0V
LOGIC 1
LOGIC 0
09616-084
Figure 164. LVDS Data Input Levels
Table 26. Example of LVDS Input Levels
Applied Voltages
Resulting
Differential
Voltage
Resulting
Common-
Mode
Voltage
Logic Bit
Binary
Equivalent
V
P
V
N
V
P, N
V
COM
1.4 V 1.0 V +0.4 V 1.2 V 1
1.0 V 1.4 V −0.4 V 1.2 V 0
1.0 V 0.8 V +200 mV 900 mV 1
0.8 V 1.0 V −200 mV 900 mV 0
MU CONTROLLER
A delay lock loop (DLL) is used to optimize the timing between
the internal digital and analog domains of the AD9737A/AD9739A
such that data is successfully transferred into the TxDAC core at
rates of up to 2.5 GSPS. As shown in Figure 165, the DAC clock
is split into an analog and a digital path with the critical analog
path leading to the DAC core (for minimum jitter degradation)
and the digital path leading to a programmable delay line. Note that
the output of this delay line serves as the master internal digital
clock from which all other internal and external digital clocks
are derived. The amount of delay added to this path is under the
control of the Mu controller, which optimizes the timing between
these two clock domains and continuously tracks any variation
(once in track mode) to ensure proper data hand-off.
14-BIT
DATA
14-BIT
DATA
IOUTP
IOUTN
DIGITAL
CIRCUITRY
ANALOG
CIRCUITRY
MU
DELAY
DAC
CLOCK
PHASE
DETECTOR
MU
DELAY
CONTROLLER
09616-085
Figure 165. AD97339A Mu Delay Controller Block Diagram
The Mu controller adjusts the timing relationship between the
digital and analog domains via a tapped digital delay line having
a nominal total delay of 864 ps. The delay value is programmable
to a 9-bit resolution (that is, 0 to 432 decimal) via the MUDEL
bits (Register 0x27 and 0x28), resulting in a nominal resolution
of 2 ps/LSB. Because a time delay maps to a phase offset for a
fixed clock frequency, the control loop essentially compares the
phase relationship between the two clock domains and adjusts
the phase (that is, via a tapped delay line) of the digital clock such
that it is at the desired fixed phase offset (SET_PHS) from the
critical analog clock.
0
2
4
6
8
10
12
14
16
18
0 40 80 120 160 200 240 280 320 360 400 440
SEARCH STARTING
LOCATION
GUARD
BAND
GUARD
BAND
MU DELAY
MU PHASE
DESIRED
PHASE
09616-086
Figure 166. Typical Mu Phase Characteristic Plot at 2.4 GSPS
Figure 166 maps the typical Mu phase characteristic at 2.4 GSPS vs.
the 9-bit digital delay setting (MUDEL). The Mu phase scaling
is such that a value of 16 corresponds to 180 degrees. The critical
keep-out window between the digital and analog domains occurs
at a value of 0 (but can extend out to 2 depending on the clock
rate). The target Mu phase (and slope) is selected to provide
optimum ac performance while ensuring that the Mu controller
for any device can establish and maintain lock. For example,
although a slope and phase setting of −6 is considered optimum
for operation between 1.6 GSPS and 2.5 GSPS, other values are
required below 1.6 GSPS.
C