Datasheet

Data Sheet AD9737A/AD9739A
Rev. | Page 57 of 64
The AD9737A/AD9739A clock receiver features the ability to
independently adjust the common-mode level of its inputs over
a span of ±100 mV centered about its mid-supply point (that is,
VDDC/2), as well as an offset for hysteresis purposes. Figure 175
shows the equivalent input circuit of one of the inputs. ESD
diodes are not shown for clarity purposes. It has been found
through characterization that the optimum setting is for both
inputs to be biased at approximately 0.8 V. This can be achieved
by writing a 0x0F (corresponding to a −15) setting to both cross
controller registers (that is, Register 0x22 and Register 0x23).
0.70
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
–15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15
OFFSET CODE
COMMON MODE (V)
CLKP
CLKN
09616-095
Figure 176. Common-Mode Voltage with Respect to
CLKP_OFFSET/CLKN_OFFSET and DIR_P/DIR_N
VOLTAGE REFERENCE
The AD9737A/AD9739A output current is set by a combination
of digital control bits and the I120 reference current, as shown
in Figure 177.
CURRENT
SCALING
FSC[9:0]
AD9737A/AD9739A
DAC
IFULL-SCALE
10kΩ
1nF
VREF
I120
VSSA
I120
V
BG
1.2V
+
–
09616-096
Figure 177. Voltage Reference Circuit
The reference current is obtained by forcing the band gap voltage
across an external 10 kΩ resistor from I120 (Pin B14) to ground.
The 1.2 V nominal band gap voltage (VREF) generates a 120 µA
reference current in the 10 kΩ resistor. Note the following
constraints when configuring the voltage reference circuit:
• Both the 10 kΩ resistor and 1 nF bypass capacitor are required
for proper operation.
• Digitally adjust the DAC’s output full-scale current, I
OUTFS
,
from its default setting of 20 mA.
• The AD9737A/AD9739A are not a multiplying DAC.
Modulating the reference current, I120, with an ac signal is
not supported.
• The band gap voltage appearing at the VREF pin (Pin C14)
must be buffered for use with an external circuitry because
its output impedance is approximately 5 kΩ.
• An external reference can be used to overdrive the internal
reference by connecting it to the VREF pin.
I
OUTFS
can be adjusted digitally over 8.7 mA to 31.7 mA by using
FSC[9:0] (Register 0x06 and Register 0x07).
The following equation relates I
OUTFS
to the FSC[9:0] bits, which
can be set from 0 to 1023.
I
OUTFS
= 22.6 × FSC[9:0]/1000 + 8.7 (1)
Note that a default value of 0x200 generates 20 mA full scale, which
is used for most of the characterization presented in this data
sheet (unless noted otherwise).
ANALOG OUTPUTS
Equivalent DAC Output and Transfer Function
The AD9737A/AD9739A provide complementary current
outputs, IOUTP and IOUTN, that source current into an external
ground reference load. Figure 178 shows an equivalent output
circuit for the DAC. Note that, compared to most current output
DACs of this type, the AD9737A/AD9739A outputs exhibit a
slight offset current (that is, I
OUTFS
/16), and the peak differential
ac current is slightly below I
OUTFS
/2 (that is, 15/32 × I
OUTFS
).
17/32 × I
OUTFS
I
PEAK
=
15/32 × I
OUTFS
AC
70Ω
2.2pF
I
OUTFS
= 8.6 – 31.2mA
17/32 × I
OUTFS
09616-097
Figure 178. Equivalent DAC Output Circuit
As shown in Figure 178, the DAC output can be modeled as a
pair of dc current sources that source a current of 17/32 × I
OUTFS
to
each output. A differential ac current source, I
PEAK,
is used to
model the signal-dependent nature of the DAC output. The
polarity and signal dependency of this ac current source are
related to the digital code by the following equation:
F(Code) = (DACCODE − 8192)/8192 (2)
−1 < F(Code) < 1 (3)
where DACCODE = 0 to 16,383 (decimal).
Because I
PEAK
can swing ±(15/32) × I
OUTFS
, the output currents
measured at IOUTP and IOUTN can span from I
OUTFS
/16 to I
OUTFS
.
However, because the ac signal-dependent current component
is complementary, the sum of the two outputs is always constant
(that is, IOUTP + IOUTN = (34/32) × I
OUTFS
).
C