Datasheet

AD9737A/AD9739A Data Sheet
Rev. | Page 6 of 64
SERIAL PORT SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V.
Table 3
.
Parameter Min Typ Max Unit
WRITE OPERATION (See Figure 154)
SCLK Clock Rate, f
SCLK
, 1/t
SCLK
20 MHz
SCLK Clock High, t
HIGH
18 ns
SCLK Clock Low, t
LOW
18 ns
SDIO to SCLK Setup Time, t
DS
2 ns
SCLK to SDIO Hold Time, t
DH
1
ns
CS to SCLK Setup Time, t
S
3 ns
SCLK to CS Hold Time, t
H
2 ns
READ OPERATION (See Figure 155 and Figure 156)
SCLK Clock Rate, f
SCLK
, 1/t
SCLK
20 MHz
SCLK Clock High, t
HIGH
18 ns
SCLK Clock Low, t
LOW
18 ns
SDIO to SCLK Setup Time, t
DS
2 ns
SCLK to SDIO Hold Time, t
DH
1 ns
CS to SCLK Setup Time, t
S
3 ns
SCLK to SDIO (or SDO) Data Valid Time, t
DV
15 ns
CS to SDIO (or SDO) Output Valid to High-Z, t
EZ
2 ns
INPUTS (SDI, SDIO, SCLK, CS)
Voltage in High, V
IH
2.0 3.3 V
Voltage in Low, V
IL
0 0.8 V
Current in High, I
IH
−10 +10 µA
Current in Low, I
IL
−10 +10 µA
OUTPUT (SDIO)
Voltage Out High, V
OH
2.4 3.5 V
Voltage Out Low, V
OL
0 0.4 V
Current Out High, I
OH
4
mA
Current Out Low, I
OL
4 mA
C