Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - ADC 16 Bit PDIP 28

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

AD974

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 1999

4-Channel, 16-Bit, 200 kSPS

Data Acquisition System

FUNCTIONAL BLOCK DIAGRAM

CONTROL LOGIC

CALIBRATION CIRCUITRY

PWRD

V1A

V1B

BIP

CAP

REF

DIG

ANA

EXT/INT

DATACLK

R/C

SYNC

DGND

BUSY

WR2

WR1

A1A0

AGND2AGND1

REF

BUFF

2.5V

REFERENCE

AD974

4 TO 1

MUX

LATCH

V2A

V2B

V3A

V3B

V4A

V4B

SWITCHED

CAP ADC

SERIAL

INTERFACE

DATA

RESISTIVE

NETWORK

RESISTIVE

NETWORK

RESISTIVE

NETWORK

RESISTIVE

NETWORK

CLOCK

FEATURES

Fast 16-Bit ADC with 200 kSPS Throughput

Four Single-Ended Analog Input Channels

Single +5 V Supply Operation

Input Ranges: 0 V to +4 V, 0 V to +5 V and ⴞ10 V

120 mW Max Power Dissipation

Power-Down Mode 50 ␮W

Choice of External or Internal 2.5 V Reference

On-Chip Clock

Power-Down Mode

GENERAL DESCRIPTION

The AD974 is a four-channel, data acquisition system with a

serial interface. The part contains an input multiplexer, a high-

speed 16-bit sampling ADC and a +2.5 V reference. All of this

operates from a single +5 V power supply that also has a power-

down mode. The part will accommodate 0 V to +4 V, 0 V to

+5 V or ±10 V analog input ranges.

The interface is designed for an efficient transfer of data while

requiring a low number of interconnects.

The AD974 is comprehensively tested for ac parameters such as

SNR and THD, as well as the more traditional parameters of

offset, gain and linearity.

The AD974 is fabricated on Analog Devices’ BiCMOS process,

which has high performance bipolar devices along with CMOS

transistors.

The AD974 is available in 28-lead DIP, SOIC and SSOP

packages.

PRODUCT HIGHLIGHTS

1. The AD974 is a complete data acquisition system combining

a four-channel multiplexer, a 16-bit sampling ADC and a

+2.5 V reference on a single chip.

2. The part operates from a single +5 V supply and also has a

power-down feature.

3. Interfacing to the AD974 is simple with a low number of

interconnect signals.

4. The AD974 is comprehensively specified for ac parameters

such as SNR and THD, as well as dc parameters such as

linearity and offset and gain errors.

Summary of content (20 pages)

PAGE 1
a FEATURES Fast 16-Bit ADC with 200 kSPS Throughput Four Single-Ended Analog Input Channels Single +5 V Supply Operation Input Ranges: 0 V to +4 V, 0 V to +5 V and ⴞ10 V 120 mW Max Power Dissipation Power-Down Mode 50 ␮W Choice of External or Internal 2.5 V Reference On-Chip Clock Power-Down Mode 4-Channel, 16-Bit, 200 kSPS Data Acquisition System AD974 FUNCTIONAL BLOCK DIAGRAM PWRD BIP VDIG REF CAP REF BUFF V1A V1B V2A V2B V3A V3B RESISTIVE NETWORK VANA 2.
PAGE 2
AD974–SPECIFICATIONS (–40ⴗC to +85ⴗC, f = 200 kHz, V S Parameter Conditions RESOLUTION ANALOG INPUT Voltage Range Impedance Sampling Capacitance AC ACCURACY Spurious Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) Signal-to-Noise Channel-to-Channel Isolation Full Power Bandwidth6 –3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Transient Response Overvoltage Recovery7 REFERENCE Internal Reference Voltage Internal Reference Source Current External Reference Voltage Range f
PAGE 3
AD974 Parameter DIGITAL OUTPUTS Data Format Data Coding VOL VOH Output Capacitance Leakage Current Conditions Min ISINK = 1.6 mA ISOURCE = 500 µA High-Z State High-Z State VOUT = 0 V to V DIG POWER SUPPLIES Specified Performance VDIG VANA IDIG IANA Power Dissipation PWRD LOW PWRD HIGH TEMPERATURE RANGE Specified Performance A Grade Typ +4 +4.75 +4.75 +5 +5 4.5 14 B Grade Min Typ Max Max Serial 16 Bits Straight Binary +0.4 +4 15 15 V V pF ±5 ±5 µA +5.25 +5.
PAGE 4
AD974 ABSOLUTE MAXIMUM RATINGS 1 PIN CONFIGURATION Analog Inputs VxA, VxB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V CAP . . . . . . . . . . . . . . . . +VANA + 0.3 V to AGND2 – 0.3 V REF . . . . . . . . . . . . . . . . . . . . Indefinite Short to AGND2, Momentary Short to VANA Ground Voltage Differences DGND, AGND1, AGND2 . . . . . . . . . . . . . . . . . . . ± 0.3 V Supply␣ Voltages VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
AD974 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 2–5, 25–28 6 7 AGND1 VxA, VxB BIP CAP 8 REF 9 10 AGND2 R/C 11 12 VDIG PWRD 13 EXT/INT 14 15 DGND SYNC 16 DATACLK 17 DATA 18, 19 WR1, WR2 20 CS 21 BUSY 22, 23 A1, A0 Analog Ground. Used as the ground reference point for the REF pin. Analog Input. Refer to Table I for input range configuration. Bipolar Offset. Connect VxA inputs to provide Bipolar input range. Reference Buffer Output. Connect a 2.
PAGE 6
AD974 DEFINITION OF SPECIFICATIONS SPURIOUS FREE DYNAMIC RANGE INTEGRAL NONLINEARITY ERROR (INL) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Linearity error refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as “negative full scale” occurs 1/2 LSB before the first code transition.
PAGE 7
AD974 CONVERSION CONTROL INTERNAL DATA CLOCK MODE The AD974 is controlled by two signals: R/C and CS. When R/C is brought low, with CS low, for a minimum of 50 ns, the input signal will be held on the internal capacitor array and a conversion “n” will begin. Once the conversion process does begin, the BUSY signal will go low until the conversion is complete. Internally, the signals R/C and CS are ORed together and there is no requirement on which signal is taken low first when initiating a conversion.
PAGE 8
AD974 EXTERNAL DISCONTINUOUS CLOCK DATA READ AFTER CONVERSION WITH NO SYNC OUTPUT GENERATED can be read after the conversion is complete. The external clock can be either a continuous or discontinuous clock. A discontinuous clock can be either normally low or normally high when inactive. In the case of the discontinuous clock, the AD974 can be configured to either generate or not generate a SYNC output (with a continuous clock a SYNC output will always be produced).
PAGE 9
AD974 EXTERNAL DISCONTINUOUS CLOCK DATA READ DURING CONVERSION WITH NO SYNC OUTPUT GENERATED discontinuous external clock, with the generation of a SYNC output. What permits the generation of a SYNC output is a transition of DATACLK while either CS is high or while both CS and R/C are low. After a conversion is complete, indicated by BUSY returning high, the result of that conversion can be read while CS is Low and R/C is high. In this mode CS can be tied low.
PAGE 10
AD974 begun. Figure 7 shows R/C then going high and after a delay of greater than 15 ns (t15 ) clock pulse #1 can be taken high to request the SYNC output. The SYNC output will appear approximately 40 ns after this rising edge and will be valid on the falling edge of clock pulse #1 and the rising edge of clock pulse #2. The MSB will be valid approximately 40 ns after the rising edge of clock pulse #2 and can be latched off either the falling edge of clock pulse #2 or the rising edge of clock pulse #3.
PAGE 11
AD974 EXTERNAL CONTINUOUS CLOCK DATA READ AFTER CONVERSION WITH SYNC OUTPUT GENERATED Figure 8 illustrates the method by which data from conversion “n” can be read after the conversion is complete using a continuous external clock, with the generation of a SYNC output. What permits the generation of a SYNC output is a transition of DATACLK either while CS is high or while both CS and R/C are low. and R/C is high. In Figure 8 clock pulse #0 is used to enable the generation of a SYNC pulse.
PAGE 12
AD974 EXTERNAL CONTINUOUS CLOCK DATA READ DURING CONVERSION WITH SYNC OUTPUT GENERATED Figure 9 illustrates the method by which data from conversion “n-1” can be read during conversion “n” while using a continuous external clock with the generation of a SYNC output. What permits the generation of a SYNC output is a transition of DATACLK either while CS is high or while both CS and R/C are low. With a continuous clock the CS pin cannot be tied low as it could be with a discontinuous clock.
PAGE 13
AD974 Table I. Analog Input Configuration Input Voltage Range Connect VxA to Connect VxB to Input Impedance ± 10 V 0 V to +5 V 0 V to +4 V BIP VIN VIN VIN GND VIN 13.7 kΩ 6.0 kΩ 6.4 kΩ Table II. Output Codes and Ideal Input Voltage Description Full-Scale Range Least Significant Bit +Full Scale (FS – 1 LSB) Midscale One LSB Below Midscale –Full Scale Digital Input Straight Binary Analog Input ± 10 V 305 µV +9.999695 V 0V –305 µV –10 V 0 V to +5 V 76 µV +4.999847 V +2.5 V +2.
PAGE 14
AD974 INPUT RANGE BASIC CONNECTIONS FOR AD974 BIP VxA VIN VxB AGND1 610V + CAP 2.2mF 2.2mF AD974 + REF AGND2 BIP VIN VxA VxB AGND1 0V TO +5V + CAP 2.2mF 2.2mF AD974 + REF AGND2 BIP VIN VxA VxB AGND1 0V TO +4V + CAP 2.2mF 2.2mF AD974 + REF AGND2 Figure 11. Analog Input Configurations –14– REV.
PAGE 15
AD974 OFFSET AND GAIN ADJUSTMENT The AD974 is factory trimmed to minimize gain, offset and linearity errors. There are no internal provisions to allow for any further adjustment of offset error through external circuitry. The reference of the AD974 can be adjusted as shown in Figure 12. This will allow the full-scale error of any one channel to be adjusted to zero or will allow the average full-scale error of the four channels to be minimized. + CAP dV ON CAP PIN – 10nV/DIV 2.
PAGE 16
AD974 100% AC PERFORMANCE 2.0 The AD974 is fully specified and tested for dynamic performance specifications. The ac parameters are required for signal processing applications such as speech recognition and spectrum analysis. These applications require information on the ADC’s effect on the spectral content of the input signal. Hence, the parameters for which the AD974 is specified include S/(N+D), THD and Spurious Free Dynamic Range. These terms are discussed in greater detail in the following sections.
PAGE 17
AD974 110 When used with an external reference, connected to the REF pin and a 2.2 µF capacitor, connected to the CAP pin, the power-up recovery time is typically 1 ms. This typical value of 1 ms for recovery time depends on how much charge has decayed from the external 2.2 µF capacitor on the CAP pin and assumes that it has decayed to zero. The 1 ms recovery time has been specified such that settling to 16 bits has been achieved.
PAGE 18
AD974 data read operation. The recommended procedure to ensure this is as follows: 0 –10 –20 • Enable SPORT0 through the System Control register. –30 • Set the SCLK Divide register to zero. –40 • Setup PF0 and PF1 as outputs by setting bits 0 and 1 in PFTYPE. dBFS –50 –60 –70 • Force RFS0 low through PF0. The Receive Frame Sync signal has been programmed active high. –80 –90 • Enable AD974 by forcing CS = 0 through PF1. –100 • Enable SPORT0 Receive Interrupt through the IMASK register.
PAGE 19
AD974 The AD974 may be operated from a single +5␣ V supply. When separate supplies are used, however, it is beneficial to have larger (10␣ µF) capacitors placed between the logic supply (VDIG ) and digital common (DGND), and between the analog supply (VANA) and the analog common (AGND2). Additionally, 10␣ µF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple.
PAGE 20
AD974 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead 300 Mil Plastic DIP (N-28B) 28 15 1 14 0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) PIN 1 0.015 (0.381) MIN 0.210 (5.33) MAX SEATING PLANE 0.022 (0.558) 0.100 (2.54) 0.070 (1.77) BSC 0.014 (0.356) 0.045 (1.15) C3273a–0–5/99 1.425 (38.195) 1.385 (35.179) 0.195 (4.95) 0.115 (2.93) 0.150 (3.81) 0.115 (2.92) 0.014 (0.356) 0.008 (0.204) 28-Lead Wide Body (SOIC) (R-28) 15 1 14 0.1043 (2.65) 0.0926 (2.35) PIN 1 0.