Datasheet

AD9761
–10–
AD9761
–11–
FUNCTIONAL DESCRIPTION
Figure 4 shows a simplied block diagram of the AD9761. The
AD9761 is a complete dual-channel, high speed, 10-bit CMOS
DAC capable of operating up to a 40 MHz clock rate. It has
been optimized for the transmit section of wideband communica-
tion systems employing I and Q modulation schemes. Excellent
matching characteristics between channels reduce the need for
any external calibration circuitry. Dual matching 2 interpola-
tion lters included in the I and Q data path simplify any post
band-limiting lter requirements. The AD9761 interfaces with a
single 10-bit digital input bus that supports interleaved I and Q
input data.
ACOM
REFLO
I
DAC
FSADJ
IOUTA
IOUTB
WRITE INPUT
SELECT INPUT
DCOM
DVDD
CLOCK
AD9761
2
LATCH
I
REFIO
REFERENCE
COMP1
COMP2
COMP3
BIAS
GENERATOR
QOUTA
QOUTB
2
LATCH
Q
MUX
CONTROL
AVDD
DAC DAT
A
INPUT
S
(10 BITS)
SLEEP
Q
DAC
Figure 4. Dual DAC Functional Block Diagram
Referring to Figure 4, the AD9761 consists of an analog sec-
tion and a digital section. The analog section includes matched
I and Q 10-bit DACs, a 1.20 V band gap voltage reference, and
a reference control amplier. The digital section includes two 2
interpolation lters, segment decoding logic, and some additional
digital input interface circuitry. The analog and digital sections of
the AD9761 have separate power supply inputs (i.e., AVDD and
DVDD) that can operate independently. The digital supply can
operate over a 2.7 V to 5.5 V range, allowing it to accommodate
TTL as well as 3.3 V and 5 V CMOS logic families. The analog
supply must be restricted from 3.0 V to 5.5 V to maintain opti-
mum performance.
Each DAC consists of a large PMOS current source array capable
of providing up to 10 mA of full-scale current, I
OUTFS
. Each array is
divided into 15 equal currents that make up the four most signi-
cant bits (MSBs). The next four bits or middle bits consist of 15
equal current sources whose values are 1/16 of an MSB current
source. The remaining LSBs are binary weighted fractions of
the middle bits’ current sources. All of these current sources are
switched to one of two output nodes (i.e., IOUTA or IOUTB)
via PMOS differential current switches.
The full-scale output current, I
OUTFS
, of each DAC is regulated
from the same voltage reference and control amplier, thus
ensuring excellent gain matching and drift characteristics
between DACs. I
OUTFS
can be set from 1 mA to 10 mA via an
external resistor, R
SET
. The external resistor in combination
with both the reference control amplier and voltage reference,
V
REFIO
, sets the reference current, I
REF
, which is mirrored over
to the segmented current sources with the proper scaling factor.
I
OUTFS
is exactly 16 times the value of I
REF
.
The I and Q DACs are simultaneously updated on the rising
edge of CLOCK with digital data from their respective 2
digital interpolation lters. The 2 interpolation lters essen-
tially multiply the input data rate of each DAC by a factor of
2, relative to its original input data rate, while simultaneously
reducing the magnitude of the rst image associated with the
DAC’s original input data rate. Since the AD9761 supports a
single 10-bit digital bus with interleaved I and Q input data, the
original I and Q input data rate before interpolation is one-half
the CLOCK rate. After interpolation, the data rate into each I
and Q DAC becomes equal to the CLOCK rate.
The benets of an interpolation lter are illustrated in Figure 5,
which shows an example of the frequency and time domain rep-
resentation of a discrete time sine wave signal before and after
it is applied to a digital interpolation lter. Images of the sine
wave signal appear around multiples of the DAC’s input data
rate as predicted by the sampling theory. These undesirable
images will also appear at the output of a reconstruction DAC,
although modied by the DAC’s sin(x)/(x) response. In many
band-limited applications, these images must be suppressed by
an analog lter following the DAC. The complexity of this ana-
FUNDAMENTAL
1
f
CLOCK
FUNDAMENTAL
DIGITAL
FILTER
SUPPRESSED
OLD
1
ST
IMAGE
NEW
1ST IMAG
E
f
CLOCK
1
ST
IMAGE
2
f
CLOCK
f
CLOCK
f
CLOCK
2
f
CLOCK
DACs
SIN(X)
X
TIME DOMAIN
FREQUENCY DOMAIN
2 INTERPOLATION FILTER
INPUT DATA LATCH
DAC
f
CLOCK
f
CLOCK
2
f
CLOCK
2
f
CLOCK
2
2
Figure 5. Time and Frequency Domain Example of Digital Interpolation Filter
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