Datasheet

AD9761
–10–
AD9761
–11–
log lter is typically determined by the proximity of the desired
fundamental to the rst image and the required amount of image
suppression.
Referring to Figure 5, the “new” rst image associated with the
DAC’s higher data rate after interpolation is “pushed” out fur-
ther relative to the input signal. The “old” rst image associated
with the lower DAC data rate before interpolation is suppressed
by the digital lter. As a result, the transition band for the analog
reconstruction lter is increased, thus reducing the complexity
of the analog lter.
The digital interpolation lters for I and Q paths are identi-
cal 43-tap half-band symmetric FIR lters. Each lter receives
de-interleaved I or Q data from the digital input interface. The
input CLOCK signal is internally divided by 2 to generate the
lter clock. The lters are implemented with two parallel paths
running at the lter clock rate. The output from each path is
selected on opposite phases of the lter clock, thus producing
interpolated ltered output data at the input clock rate. The
frequency response and impulse response of these lters are
shown in Figures 2a and 2b. Table I lists the idealized lter
coefcients that correspond to the lter’s impulse response.
The digital section of the AD9761 also includes an input interface
section designed to support interleaved I and Q input data from
a single 10-bit bus. This section de-interleaves the I and Q input
data while ensuring its proper pairing for the 2 interpolation
lters. A RESET/SLEEP input serves a dual function by providing
a reset function for this section as well as providing power-down
functionality. Refer to the Digital Inputs and Interleaved Interface
Considerations and RESET/SLEEP Mode Operation sections for
a more detailed discussion.
DAC TRANSFER FUNCTION
Each I and Q DAC provides complementary current output
pins: IOUT(A/B) and QOUT(A/B), respectively. Note that
QOUTA and QOUTB operate identically to IOUTA and
IOUTB. IOUTA will provide a near full-scale current output,
I
OUTFS
, when all bits are high (i.e., DAC CODE = 1023), while
IOUTB, the complementary output, provides no current. The
current outputs of IOUTA and IOUTB are a function of both
the input code and I
OUTFS
and can be expressed as
I DAC CODE/ I
OUTA OUTFS
=
( )
×1024
(1)
I – DAC CODE I
OUTB OUTFS
=
( )
×1023 1024/
(2)
where:
DAC CODE = 0 to 1023 (i.e., decimal representation).
As previously mentioned, I
OUTFS
is a function of the reference
current, I
REF
, which is nominally set by a reference, V
REFIO
, and
external resistor, R
SET
. It can be expressed as
I I
OUTFS REF
= ×16
(3)
where:
I V R
REF REFIO SET
= /
(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, R
LOAD
, which are tied to analog common, ACOM. Note
that R
LOAD
represents the equivalent load resistance seen by
IOUTA or IOUTB. The single-ended voltage output appearing
at IOUTA and IOUTB pins is simply
V I R
IOUTA OUTA LOAD
= ×
(5)
V I R
IOUTB OUTB LOAD
= ×
(6)
Note that the full-scale value of V
IOUTA
and V
IOUTB
should not
exceed the specied output compliance range to maintain speci-
ed distortion and linearity performance.
The differential voltage, V
IDIFF
, appearing across IOUTA and
IOUTB is
V I I R
IDIFF IOUTA IOUTB LOAD
=
( )
×–
(7)
Substituting the values of I
IOUTA
, I
IOUTB
, and I
REF
, V
IDIFF
can be
expressed as
V DAC CODE –
R R
V
IDIFF
LOAD SET REFIO
=
( )
)
{ }
×
( )
×
2 1023 1024
16
/
/
(8)
These last two equations highlight some of the advantages of
operating the AD9761 differentially. First, differential opera-
tion will help cancel common-mode error sources associated
with I
IOUTA
and I
IOUTB
, such as noise and distortion. Second,
the differential code-dependent current and subsequent volt-
age, V
IDIFF
, is twice the value of the single-ended voltage output
(i.e., V
IOUTA
or V
IOUTB
), thus providing twice the signal power to
the load.
REFERENCE OPERATION
The AD9761 contains an internal 1.20 V band gap reference that
can be easily disabled and overridden by an external reference.
REFIO serves as either an input or output depending on whether
the internal or an external reference is selected. If REFLO is tied
to ACOM as shown in Figure 6, the internal reference is activated
and REFIO provides a 1.20 V output. In this case, the internal ref-
erence must be ltered externally with a ceramic chip capacitor of
0.1 µF or greater from REFIO to REFLO. Also, REFIO should be
buffered with an external amplier having a low input bias current
(i.e., <1 µA) if any additional loading is required.
50pF
CURRENT
SOURCE
ARRAY
+1.2V REF
REFIO
FSADJ
REFLO COMP2 AVDD
0.1F
R
SET
2k
0.1F
OPTIONAL EXTERNAL
REF BUFFER FOR
ADDITIONAL LOADS
COMPENSATION
CAPACITOR
REQUIRE
D
AD9761
Figure 6. Internal Reference Conguration
The internal reference can also be disabled by connecting
REFLO to AVDD. In this case, an external reference may then
be applied to REFIO as shown in Figure 7. The external reference
may provide either a xed reference voltage to enhance accura-
cy and drift performance or a varying reference voltage for gain
control. Note that the 0.1 µF compensation capacitor is not
required since the internal reference is disabled and the high
input impedance (i.e., 1 M) of REFIO minimizes any loading
of the external reference.
REV. C
REV. C