Datasheet

AD9761
–12–
AD9761
–13–
50pF
CURRENT
SOURCE
ARRAY
+1.2V REF
REFIO
FSADJ
REFLO COMP2 AVDD
I
REF
=
V
REF
/R
SET
AVDD
R
SET
EXT.
V
REF
AVDD
0.1F
AD9761
+
–
Figure 7. External Reference Conguration
REFERENCE CONTROL AMPLIFIER
The AD9761 also contains an internal control amplier that is
used to simultaneously regulate both DACs’ full-scale out put
current, I
OUTFS
. Since the I and Q I
OUTFS
are derived from
the same voltage reference and control circuitry, ex cellent
gain matching is ensured. The control amplier is congured
as a V-I converter as shown in Figure 7 such that its current
output, I
REF
, is determined by the ratio of the V
REFIO
and an
external resistor, R
SET
, as stated in Equation 4. I
REF
is cop ied
over to the segmented current sources with the proper scal ing
factor to set I
OUTFS
as stated in Equation 3.
The control amplier allows a wide (10:1) adjustment span
of I
OUTFS
over a 1 mA to 10 mA range by setting I
REF
be tween
62.5 µA and 625 µA. The wide adjustment span of I
OUTFS
provides several application benets. The rst benet relates
directly to the power dissipation of the AD9761’s analog
supply, AVDD, which is proportional to I
OUTFS
(refer to the
Power Dissipation section). The second benet relates to the
20 dB adjustment span, which may be useful for sys tem gain
control purposes.
Optimum noise and dynamic performance for the AD9761 is
obtained with a 0.1 µF external capacitor installed be tween
COMP2 and AVDD. The bandwidth of the reference control
amplier is limited to approximately 5 kHz with a 0.1 µF
capacitor installed. Since the –3 dB bandwidth corresponds
to the dominant pole and therefore its dominant time con-
stant, the settling time of the control amplier to a stepped
refer ence input response can be easily determined. Note that
the output of the control amplier, COMP2, is internally
compensated via a 50 pF capacitor, thus ensuring its stabil-
ity if no external capacitor is added.
Depending on the requirements of the application, I
REF
can be adjusted by varying either R
SET
, or, in the external
reference mode, by varying the REFIO voltage. I
REF
can be
varied for a xed R
SET
by disabling the internal reference and
varying the voltage of REFIO over its compliance range of
1.25 V to 0.10 V. REFIO can be driven by a single-supply
amplier or DAC, thus allowing I
REF
to be varied for a xed
R
SET
. Since the input impedance of REFIO is approximately
1 M, a simple, low cost R-2R ladder DAC congured in
the voltage mode topology may be used to control the gain.
This circuit is shown in Figure 8 using the AD7524 and an
external 1.2 V reference, the AD1580.
ANALOG OUTPUTS
As previously stated, both the I and Q DACs produce two
complementary current outputs that may be congured for
single-ended or differential operation. I
IOUTA
and I
IOUTB
can be
converted into complementary single-ended voltage outputs,
V
IOUTA
and V
IOUTB
, via a load resistor, R
LOAD
, as described in
the DAC Transfer Function section by Equations 5 through
8. The differential voltage, V
IDIFF
, existing between V
IOUTA
and V
IOUTB
, can also be converted to a single-ended voltage
via a transformer or differential amplier conguration.
Figure 9 shows an equivalent circuit of the AD9761’s I (or Q)
DAC output. It consists of a parallel array of PMOS current
sources in which each current source is switched to either
IOUTA or IOUTB via a differential PMOS switch. As a re sult,
the equivalent output impedance of IOUTA and IOUTB
remains quite high (i.e., >100 k and 5 pF).
AD9761
AVDD
R
LOAD
R
LOAD
IOUTA IOUTB
Figure 9. Equivalent Circuit of the AD9761 DAC Output
IOUTA and IOUTB have a negative and positive voltage
compliance range that must be adhered to achieve optimum
performance. The negative output compliance range of –1 V is
set by the breakdown limits of the CMOS process. Operation
beyond this maximum limit may result in a breakdown of the
output stage.
50pF
CURRENT
SOURCE
ARRAY
+1.2V REF
REFIO
FSADJ
REFLO COMP2 AVDD
AVDD
AD1580
1.2V
OPTIONAL
BAND LIMITING
CAPACITOR
I
REF
=
V
REF
/R
SET
AVDD
R
SET
0.1V TO 1.2V
R
FB
V
DD
OUT1
OUT2
AGND
V
REF
AD7524
DB7–DB0
+
–
AD9761
Figure 8. Single-Supply Gain Control Circuit
REV. C
REV. C