Datasheet

–2–
AD9761–SPECIFICATIONS
AD9761
–3–
DYNAMIC SPECIFICATIONS
(T
MIN
to T
MAX
, AVDD = 5 V, DVDD = 5 V, I
OUTFS
= 10 mA, Differential Transformer Coupled Output,
50  Doubly Terminated, unless otherwise noted.)
DIGITAL SPECIFICATIONS
(T
MIN
to T
MAX
, AVDD = 5 V, DVDD = 5 V, I
OUTFS
= 10 mA unless otherwise noted.)
Parameter Min Typ Max Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate 40 MSPS
Output Settling Time (t
ST
to 0.025%) 35 ns
Output Propagation Delay (t
PD
) 55 Input Clock Cycles
Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%) 2.5 ns
Output Fall Time (10% to 90%) 2.5 ns
AC LINEARITY TO NYQUIST
Signal-to-Noise and Distortion (SINAD)
f
OUT
= 1 MHz; CLOCK = 40 MSPS 56 59 dB
Effective Number of Bits (ENOBs) 9.0 9.5 Bits
Total Harmonic Distortion (THD)
f
OUT
= 1 MHz; CLOCK = 40 MSPS
T
A
= 25°C –68 –58 dB
T
MIN
to T
MAX
–67 –53 dB
Spurious-Free Dynamic Range (SFDR)
f
OUT
= 1 MHz; CLOCK = 40 MSPS; 10 MHz Span 59 68 dB
Channel Isolation
f
OUT
= 8 MHz; CLOCK = 40 MSPS; 10 MHz Span 90 dBc
Specications subject to change without notice.
Parameter Min Typ Max Unit
DIGITAL INPUTS
Logic 1 Voltage @ DVDD = 5 V 3.5 5 V
Logic 1 Voltage @ DVDD = 3 V 2.4 3 V
Logic 0 Voltage @ DVDD = 5 V 0 1.3 V
Logic 0 Voltage @ DVDD = 3 V 0 0.9 V
Logic 1 Current –10 +10 µA
Logic 0 Current –10 +10 µA
Input Capacitance 5 pF
Input Setup Time (t
S
) 3 ns
Input Hold Time (t
H
) 2 ns
CLOCK High 5 ns
CLOCK Low 5 ns
Invalid CLOCK/WRITE Window (t
CINV
)* 1 5 ns
*t
CINV
is an invalid window of 4 ns duration beginning 1 ns after the rising edge of WRITE in which the rising edge of CLOCK must not occur.
Specications subject to change without notice.
I DATA Q DATA
t
CINV
DB9–DB0
DAC
INPUTS
SELECT
WRITE
CLOCK
t
S
t
H
NOTE: WRITE AND CLOCK CAN BE
TIED TOGETHER. FOR TYPICAL EXAMPLES,
REFER TO DIGITAL INPUTS AND INTERLEAVED
INTERFACE CONSIDERATION SECTION.
Figure 1. Timing Diagram
REV. C
REV. C