Datasheet

Data Sheet AD9763/AD9765/AD9767
Rev. G | Page 21 of 44
THEORY OF OPERATION
5
V
CLK1/IQCLK CLK2/IQRESET
AVDD
FSADJ1
REFIO
FSADJ2
1.2V REF
CHANNEL 1 LATCH
CHANNEL 2 LATCH
MODE
MULTIPLEXING LOGIC
5V
GAINCTRL
ACOM
SLEEP
AD9763/
AD9765/
AD9767
R
SET
1
2kΩ
0.1µF
R
SET
2
2kΩ
CLK
DIVIDER
DAC1
LATCH
PMOS
CURRENT
SOURCE
ARRAY
PMOS
CURRENT
SOURCE
ARRAY
WRT1/
IQWRT
RETIMED CLOCK OUTPUT*
LECROY 9210
PULSE
GENERATOR
50Ω
DIGITAL
DATA
TEKTRONIX
AWG2021
w/OPTION 4
WRT2/
IQSEL
*AWG2021 CLOCK RETIMED SUCH THAT
DIGITAL DATA TRANSITIONS ON FALLING
EDGE OF 50% DUTY CYCLE CLOCK.
PORT 1 PORT 2
I
OUTA1
I
OUTB1
I
OUTA2
I
OUTB2
DAC2
LATCH
LSB
SWITCH
SEGMENTED
SWITCHES FOR
DAC2
SEGMENTED
SWITCHES FOR
DAC1
LSB
SWITCH
TO HP3589A
OR EQUIVALENT
SPECTRUM/
NETWORK
ANALYZER
Mini-Circuits
T1-1T
50Ω 50Ω
00617-057
DVDD1/
DVDD2
DCOM1/
DCOM2
DVDD1/DVDD2
DCOM1/DCOM2
Figure 57. Basic AC Characterization Test Setup for AD9763/AD9765/AD9767,
Testing Port 1 in Dual-Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2
0.1µF
5
V
CLK1/IQCLK CLK2/IQRESET
AVDD
FSADJ1
REFIO
FSADJ2
1.2V REF
CHANNEL 1 LATCH CHANNEL 2 LATCH
MODE
MULTIPLEXING LOGIC
5V
GAINCTRL
SLEEP
ACOM
DIGITAL DATA INPUTS
NOTES
1. IN THIS CONFIGURATION, THE 22nF CAPACITOR AND 256Ω RESISTOR ARE NOT REQUIRED BECAUSE R
SET
= 2kΩ.
R
SET
1
2kΩ
I
REF
1
R
SET
2
2kΩ
I
REF
2
WRT1/
IQWRT
WRT2/
IQSEL
I
OUTB2
I
OUTA2
I
OUTB1
I
OUTA1
PMOS
CURRENT
SOURCE
ARRAY
PMOS
CURRENT
SOURCE
ARRAY
CLK
DIVIDER
DAC1
LATCH
DAC2
LATCH
SEGMENTED
SWITCHES FOR
DAC1
LSB
SWITCH
SEGMENTED
SWITCHES FOR
DAC2
LSB
SWITCH
V
DIFF
= V
OUT
A – V
OUT
B
V
OUT
1A
V
OUT
1B
V
OUT
2A
V
OUT
2B
R
L
1A
50Ω
R
L
1B
50Ω
R
L
2A
50Ω
R
L
2B
50Ω
00617-058
PORT 1 PORT 2
DVDD1/
DVDD2
DCOM1/
DCOM2
AD9763/
AD9765/
AD9767
Figure 58. Simplified Block Diagram
FUNCTIONAL DESCRIPTION
Figure 58 shows a simplified block diagram of the AD9763/
AD9765/AD9767. The AD9763/AD9765/AD9767 consist of
two DACs, each one with its own independent digital control
logic and full-scale output current control. Each DAC contains
a PMOS current source array capable of providing up to 20 mA
of full-scale current (I
OUTFS
).
The array is divided into 31 equal currents that make up the five
most significant bits (MSBs). The next four bits, or middle bits,
consist of 15 equal current sources whose value is 1/16th
of an
MSB current source. The remaining LSB is a binary weighted
fraction of the middle bit current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances the dynamic performance for multitone or low
amplitude signals and helps maintain the high output impedance
of each DAC (that is, >100 k).
All of these current sources are switched to one of the two
output nodes (that is, I
OUTA
or I
OUTB
) via the PMOS differential
current switches. The switches are based on a new architecture
that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the
differential current switches.
The analog and digital sections of the AD9763/AD9765/AD9767
have separate power supply inputs (that is, AVDD and DVDD1/
DVDD2) that can operate independently at 3.3 V or 5 V. The
digital section, which is capable of operating up to a 125 MSPS
clock rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V band gap
voltage reference, and two reference control amplifiers.