Datasheet

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AD9775

Rev. E | Page 46 of 56

SIGNAL GENERATOR

CLK+/CLK–DATACLK

LECROY

PULSE

GENERATOR

TRIG

INP

AWG2021

DG2020

INPUT CLOCK

DAC1, DB13–DB0

AD9775

DAC2, DB13–DB0

40-PIN RIBBON CABLE

JUMPER CONFIGURATION FOR TWO-PORT MODE PLL OFF

JP1 –

JP2 –

JP3 –

JP5 –

JP6 –

JP12 –

JP24 –

JP25 –

JP26 –

JP27 –

JP31 –

JP32 –

JP33 –

SOLDERED/IN

UNSOLDERED/OUT

02858-103

NOTES

1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.

2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25

AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT

PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. SEE THE TWO-PORT DATA INPUT MODE

FOR MORE INFORMATION.

Figure 103. Test Configuration for AD9775 in Two-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency,

DATACLK = Signal Generator Frequency/Interpolation Rate

SIGNAL GENERATOR

CLK+/CLK–ONEPORTCLK

LECROY

PULSE

GENERATOR

TRIG

INP

AWG2021

DG2020

INPUT CLOCK

DAC1, DB13–DB0

AD9775

DAC2, DB13–DB0

JUMPER CONFIGURATION FOR ONE-PORT MODE PLL OFF

JP1 –

JP2 –

JP3 –

JP5 –

JP6 –

JP12 –

JP24 –

JP25 –

JP26 –

JP27 –

JP31 –

JP32 –

JP33 –

SOLDERED/IN

UNSOLDERED/OUT

02858-104

NOTES

1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.

Figure 104. Test Configuration for AD9775 in One-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency,

ONEPORTCLK = Interleaved Input Data Rate = 2× Signal Generator Frequency/Interpolation Rate