Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD9826KRSZ

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties that

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

AD9826

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 www.analog.com

Fax: © Analog Devices, Inc.,

Complete 16-Bit Imaging

Signal Processor

FUNCTIONAL BLOCK DIAGRAM

OEB

DOUT

SCLK

SLOAD

SDATA

ADCCLKCDSCLK2CDSCLK1

OFFSET

VINB

VING

VINR

AV DD AV SS

CML

CAPT

AV DD

AVSS

BANDGAP

REFERENCE

AD9826

DRVDD DRVSS

GAIN

REGISTERS

OFFSET

REGISTERS

3:1

MUX

16:8

MUX

16-BIT

ADC

DIGITAL

CONTROL

INTERFACE

CONFIGURATION

RED

GREEN

BLUE

MUX

RED

GREEN

BLUE

PGA

CDS

9-BIT

DAC

CDS

9-BIT

DAC

CDS

9-BIT

DAC

INPUT

CLAMP

BIAS

CAPB

FEATURES

16-Bit 15 MSPS A/D Converter

3-Channel 16-Bit Operation up to 15 MSPS

1-Channel 16-Bit Operation up to 12.5 MSPS

2-Channel Mode for Mono Sensors with Odd/Even Outputs

Correlated Double Sampling

1~6ⴛ Programmable Gain

ⴞ300 mV Programmable Offset

Input Clamp Circuitry

Internal Voltage Reference

Multiplexed Byte-Wide Output

Optional Single Byte Output Mode

3-Wire Serial Digital Interface

3 V/5 V Digital I/O Compatibility

28-Lead SSOP Package

Low Power CMOS: 400 mW (Typ)

Power-Down Mode Available

APPLICATIONS

Flatbed Document Scanners

Digital Copier

Multifunction Peripherals

Infrared Imaging Applications

Machine Vision

PRODUCT DESCRIPTION

The AD9826 is a complete analog signal processor for imaging

applications. It features a 3-channel architecture designed to

sample and condition the outputs of trilinear color CCD arrays.

Each channel consists of an input clamp, Correlated Double

Sampler (CDS), offset DAC, and Programmable Gain Amplifier

(PGA), multiplexed to a high-performance 16-bit A/D converter.

The AD9826 can operate at speeds greater than 15 MSPS with

reduced performance.

The CDS amplifiers may be disabled for use with sensors that

do not require CDS, such as Contact Image Sensors (CIS),

CMOS active pixel sensors, and Focal Plane Arrays.

The 16-bit digital output is multiplexed into an 8-bit output word,

which is accessed using two read cycles. There is an optional

single byte output mode. The internal registers are programmed

through a 3-wire serial interface, and provide adjustment of

the gain, offset, and operating mode.

The AD9826 operates from a single 5 V power supply, typically

consumes 400 mW of power, and is packaged in a 28-lead SSOP.

REV. B





Summary of content (20 pages)

PAGE 1
a Complete 16-Bit Imaging Signal Processor AD9826 FEATURES 16-Bit 15 MSPS A/D Converter 3-Channel 16-Bit Operation up to 15 MSPS 1-Channel 16-Bit Operation up to 12.
PAGE 2
AD9826–SPECIFICATIONS ANALOG SPECIFICATIONS (TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS Mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz, PGA Gain = 1, Input range = 4 V p-p, unless otherwise noted.
PAGE 3
AD9826 DIGITAL SPECIFICATIONS (TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS Mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz, CL = 10 pF, unless otherwise noted.) Parameter Symbol Min LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance VIH VIL IIH IIL CIN 2.0 LOGIC OUTPUTS High Level Output Voltage Low Level Output Voltage High Level Output Current Low Level Output Current VOH VOL IOH IOL 4.
PAGE 4
AD9826 ABSOLUTE MAXIMUM RATINGS* Parameter VIN, CAPT, CAPB Digital Inputs AVDD DRVDD AVSS Digital Outputs Junction Temperature Storage Temperature Lead Temperature (10 sec) With Respect To Min Max AVSS AVSS AVSS DRVSS DRVSS DRVSS –0.3 –0.3 –0.5 –0.5 –0.3 –0.3 –65 AVDD + 0.3 AVDD + 0.3 +6.5 +6.5 +0.3 DRVDD + 0.3 150 +150 300 Unit V V V V V V °C °C °C THERMAL CHARACTERISTICS Thermal Resistance 28-Lead 5.
PAGE 5
AD9826 PIN CONFIGURATION CDSCLK1 1 28 AVDD CDSCLK2 2 27 AVSS ADCCLK 3 26 VINR OEB 4 25 OFFSET DRVDD 5 24 VING DRVSS 6 (MSB) D7 7 AD9826 23 CML D6 22 VINB TOP VIEW 8 (Not to Scale) 21 CAPT D5 9 20 CAPB D4 10 19 AVSS D3 11 18 AVDD D2 12 17 SLOAD D1 13 16 SCLK (LSB) D0 14 15 SDATA PIN FUNCTION DESCRIPTIONS Pin No.
PAGE 6
AD9826 INPUT REFERRED NOISE DEFINITIONS OF SPECIFICATIONS INTEGRAL NONLINEARITY (INL) Integral nonlinearity error refers to the deviation of each individual code from a line drawn from “zero scale” through “positive full scale.” The point used as “zero scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.
PAGE 7
Typical Performance Characteristics–AD9826 20 1.0 10 0.5 0 0 –10 –0.5 –1.0 –20 0 12000 24000 36000 48000 64000 0 400 600 800 1000 TPC 1. Typical INL Performance at 15 MSPS TPC 4. Typical INL Performance at 30 MSPS 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 0 12000 24000 36000 48000 0 64000 10 400 600 800 1000 10 NOISE – LSB RMS NOISE – LSB RMS 200 TPC 5. Typical DNL Performance at 30 MSPS TPC 2.
PAGE 8
AD9826 TIMING DIAGRAMS ANALOG INPUTS PIXEL n (R,G,B) tAD PIXEL (n+2) PIXEL (n+1) tAD tC1 tPRA tC2C1 CDSCLK1 tC2 tC1C2 tC2ADF CDSCLK2 tADCLK tADC2 tC2ADR ADCCLK tOD tADCLK OUTPUT DATA D<7:0> R(n–2) G(n–2) G(n–2) B(n–2) B(n–2) R(n–1) R(n–1) G(n–1) G(n–1) HIGH BYTE LOW BYTE HB LB HB LB HB LB B(n–1) HB B(n–1) R(n) R(n) G(n) G(n) LB HB LB HB LB Figure 1.
PAGE 9
AD9826 ANALOG INPUTS PIXEL n tAD PIXEL (n+2) PIXEL (n+1) tAD tC1 tPRA tC2C1 CDSCLK1 tC1C2 tC2 CDSCLK2 tC2ADR tADC2 tC2ADF ADCCLK tADCLK OUTPUT DATA D<7:0> tADCLK CH1(n–2) HIGH BYTE CH2(n–2) LOW BYTE CH1(n–1) HIGH BYTE HIGH BYTE LOW BYTE CH1(n) CH2(n–1) LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE Figure 3.
PAGE 10
AD9826 PIXEL n (R,G,B) PIXEL (n+1) tAD ANALOG INPUTS tPRA tC2 tC2AD CDSCLK2 tADC2 tADCLK tC2ADR ADCCLK tOD tADCLK OUTPUT DATA D<7:0> R (n–2) G (n–2) G (n–2) B (n–2) B (n–2) R (n–1) R (n–1) G (n–1) G (n–1) B (n–1) B (n–1) R (n) R (n) G (n) G (n) HIGH BYTE LOW BYTE HB LB HB LB HB LB HB LB HB LB HB LB Figure 5.
PAGE 11
AD9826 ADCCLK tOD tOD OUTPUT DATA HIGH BYTE DB15–DB8 LOW BYTE DB7–DB0 PIXEL n HB n+1 LB n+1 PIXEL n LB n+2 HB n+3 tDV tHZ OEB Figure 7. Digital Output Data Timing ADCCLK tOD OUTPUT DATA HIGH BYTE DB15–DB8 HIGH BYTE DB15–DB8 PIXEL n PIXEL n+1 HB n+2 tHZ tDV OEB Figure 8. Single Byte Mode Digital Output Data Timing SDATA R/Wb A2 A1 A0 D8 D7 D6 D5 D4 D3 D2 D1 D0 tDS tDH SCLK tLS tLH SLOAD Figure 9.
PAGE 12
AD9826 ANALOG INPUTS PIXEL (n+1) PIXEL n (R,G,B) CDSCLK1 CDSCLK2 ADCCLK RED PGA OUT GREEN PGA OUT BLUE PGA OUT MUX OUT OUTPUT DATA D<7:0> RED (n–1) RED (n) RED (n+1) GREEN (n–1) GREEN (n) GREEN (n+1) BLUE (n–1) BLUE (n) BLUE (n+1) GREEN (n–1) R(n–2) BLUE (n–1) RED (n) GREEN (n) RED (n+1) BLUE (n) GREEN (n+1) G(n–2) G(n–2) B(n–2) B(n–2) R(n–1) R(n–1) G(n–1) G(n–1) B(n–1) B(n–1) R(n) R(n) G(n) G(n) HIGH BYTE LOW BYTE HB LB HB LB HB LB HB LB HB LB HB LB NO
PAGE 13
AD9826 FUNCTIONAL DESCRIPTION 2-Channel CDS Mode The AD9826 can be operated in six different modes: 3-Channel CDS Mode, 3-Channel SHA Mode, 2-Channel CDS Mode, 2-Channel SHA Mode, 1-Channel CDS Mode, and 1-Channel SHA Mode. Each mode is selected by programming the Configuration Registers through the serial interface. For more detail on CDS or SHA mode operation, see the Circuit Operation section.
PAGE 14
AD9826 adjust pin. A voltage applied to this pin will be subtracted from the voltages applied to the Red, Green, and Blue inputs in the first amplifier stage of the AD9826. The input clamp is disabled in this mode. For more information, see the Circuit Operation section. Timing for this mode is shown in Figure 4. CDSCLK1 should be grounded in this mode. The rising edge of CDSCLK2 should not occur before the previous falling edge of ADCCLK, as shown by tADC2. The output data latency is three ADCCLK cycles.
PAGE 15
AD9826 MUX Configuration Register PGA Gain Registers The MUX Configuration Register controls the sampling channel order and the 2-Channel Mode configuration in the AD9826. Bits D8 and D3–D0 should always be set low. Bit D7 is used when operating in 3-Channel or 2-Channel Mode. Setting Bit D7 high will sequence the MUX to sample the Red channel first, then the Green channel, and then the Blue channel.
PAGE 16
AD9826 External Input Coupling Capacitors CIRCUIT OPERATION Analog Inputs—CDS Mode Operation Figure 12 shows the analog input configuration for the CDS mode of operation. Figure 13 shows the internal timing for the sampling switches. The CCD reference level is sampled when CDSCLK1 transitions from high to low, opening S1. The CCD data level is sampled when CDSCLK2 transitions from high to low, opening S2.
PAGE 17
AD9826 Analog Inputs—SHA Mode Operation Figure 14 shows the analog input configuration for the SHA mode of operation. Figure 15 shows the internal timing for the sampling switches. The input signal is sampled when CDSCLK2 transitions from high to low, opening S1. The voltage on the OFFSET pin is also sampled on the falling edge of CDSCLK2, when S2 opens. S3 is then closed, generating a differential output voltage representing the difference between the sampled input voltage and the OFFSET voltage.
PAGE 18
AD9826 Programmable Gain Amplifiers APPLICATIONS INFORMATION The AD9826 uses one Programmable Gain Amplifier (PGA) for each channel. Each PGA has a gain range from 1× (0 dB) to 6.0× (15.56 dB), adjustable in 64 steps. Figure 17 shows the PGA gain as a function of the PGA register code.
PAGE 19
AD9826 OUTLINE DIMENSIONS 10.50 10.20 9.90 15 28 5.60 5.30 5.00 1 8.20 7.80 7.40 14 0.65 BSC 0.38 0.22 SEATING PLANE 8° 4° 0° COMPLIANT TO JEDEC STANDARDS MO-150-AH 0.95 0.75 0.55 060106-A 0.05 MIN COPLANARITY 0.10 0.25 0.09 1.85 1.75 1.65 2.00 MAX Figure 19. 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters Revision History Location Page Data Sheet changed from REV. 0 to REV. A. Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 20
AD9826 ORDERING GUIDE Model1 AD9826KRSZ AD9826KRSZRL 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 28-Lead Shrink Small Outline Package [SSOP] 28-Lead Shrink Small Outline Package [SSOP] Z = RoHS Compliant Part. ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.